From patchwork Mon Nov 11 09:12:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13870438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82AF1D2E9C9 for ; Mon, 11 Nov 2024 09:10:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 11E6C10E44C; Mon, 11 Nov 2024 09:10:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MZr2lvcu"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6767710E44D; Mon, 11 Nov 2024 09:10:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731316206; x=1762852206; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vUG+60MVddMhTQq/iU6OQlc8CDIYxv7B7YVybT3P+ZM=; b=MZr2lvcuj/D4yNxSWAvRpJc20dvJbcU8VXBgnTkJEksK6LGrIY/JjeK5 SlLbN8CpFZ61v/vrvN68y6lSpwbsJU7DldIpcVoShpqiZ1sgZ8nV4wvx4 Oabu+9Ggb6L41Xlgfh5lpGkWu3BAQcdS8yLbA9Ilo6VLLBdbyl/GV4Ih1 0Mlk9U8jsx/nln2SFvBCCx8btu0oakx0bI/Z5Sc5AlbODg/9KF2S40FcX UKro29ZsV38Ju6/5An83YbU/K+E66DRmELrrdDSLzNqO2wkGa1HfsxEyl Yy//3UK+5YYSB3pqlL02upYd65ml7Ybs4313sjEYlBTJeUdMcZ6yuZHxh A==; X-CSE-ConnectionGUID: /vreoCmITfS1of4hiDCRcA== X-CSE-MsgGUID: 5ZVmWoFjS1i+BwAJsuA38A== X-IronPort-AV: E=McAfee;i="6700,10204,11252"; a="35052332" X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="35052332" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2024 01:10:05 -0800 X-CSE-ConnectionGUID: PbyY4qSXSr2IR2mGhMuk0Q== X-CSE-MsgGUID: 4RFIdup4T5mJ0XoEZXC6YA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="86762590" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2024 01:10:03 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 06/23] drm/i915/display: Absorb cmrr attributes into vrr Date: Mon, 11 Nov 2024 14:42:04 +0530 Message-ID: <20241111091221.2992818-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241111091221.2992818-1-ankit.k.nautiyal@intel.com> References: <20241111091221.2992818-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since cmrr is now as a mode of operation of VRR timing generator, move its elements in the vrr struct. Replace cmrr.enable with vrr.mode INTEL_VRRTG_MODE_CMRR and move cmrr_m and cmrr_n in vrr struct. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 19 +++++--------- .../drm/i915/display/intel_display_types.h | 7 +---- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_vrr.c | 26 +++++++++---------- 4 files changed, 20 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 05afcf6b21bf..4b39692f57f6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1108,14 +1108,9 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin || old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax || old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband || - old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full; -} - -static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, - const struct intel_crtc_state *new_crtc_state) -{ - return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || - old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; + old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full || + old_crtc_state->vrr.cmrr_m != new_crtc_state->vrr.cmrr_m || + old_crtc_state->vrr.cmrr_n != new_crtc_state->vrr.cmrr_n; } static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, @@ -5760,9 +5755,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_I(vrr.vsync_start); PIPE_CONF_CHECK_I(vrr.vsync_end); - PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); - PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); - PIPE_CONF_CHECK_BOOL(cmrr.enable); + PIPE_CONF_CHECK_LLI(vrr.cmrr_m); + PIPE_CONF_CHECK_LLI(vrr.cmrr_n); } #undef PIPE_CONF_CHECK_X @@ -7183,8 +7177,7 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_crtc_needs_fastset(new_crtc_state)) icl_set_pipe_chicken(new_crtc_state); - if (vrr_params_changed(old_crtc_state, new_crtc_state) || - cmrr_params_changed(old_crtc_state, new_crtc_state)) + if (vrr_params_changed(old_crtc_state, new_crtc_state)) intel_vrr_set_transcoder_timings(new_crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 48a12007bce1..2ff75d70ccda 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1294,14 +1294,9 @@ struct intel_crtc_state { u16 flipline, vmin, vmax, guardband; u32 vsync_end, vsync_start; enum intel_vrrtg_mode mode; + u64 cmrr_n, cmrr_m; /* Content Match Refresh Rate M and N */ } vrr; - /* Content Match Refresh Rate state */ - struct { - bool enable; - u64 cmrr_n, cmrr_m; - } cmrr; - /* Stream Splitter for eDP MSO */ struct { bool enable; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index eed92f83d429..fec720bcd296 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2809,7 +2809,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, as_sdp->length = 0x9; as_sdp->duration_incr_ms = 0; - if (crtc_state->cmrr.enable) { + if (crtc_state->vrr.mode == INTEL_VRRTG_MODE_CMRR) { as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; as_sdp->vtotal = adjusted_mode->vtotal; as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 23c3b555279b..83b11f3d5eb5 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -151,12 +151,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) multiplier_n = 1000; } - crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal, - multiplier_n); + crtc_state->vrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal, + multiplier_n); vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n), - crtc_state->cmrr.cmrr_n); + crtc_state->vrr.cmrr_n); adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m); - crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); + crtc_state->vrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr_n); return vtotal; } @@ -165,7 +165,6 @@ static void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) { crtc_state->vrr.tg_enable = true; - crtc_state->cmrr.enable = true; crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR; /* * TODO: Compute precise target refresh rate to determine @@ -334,15 +333,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } - if (crtc_state->cmrr.enable) { + if (crtc_state->vrr.mode == INTEL_VRRTG_MODE_CMRR) { intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), - upper_32_bits(crtc_state->cmrr.cmrr_m)); + upper_32_bits(crtc_state->vrr.cmrr_m)); intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), - lower_32_bits(crtc_state->cmrr.cmrr_m)); + lower_32_bits(crtc_state->vrr.cmrr_m)); intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), - upper_32_bits(crtc_state->cmrr.cmrr_n)); + upper_32_bits(crtc_state->vrr.cmrr_n)); intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), - lower_32_bits(crtc_state->cmrr.cmrr_n)); + lower_32_bits(crtc_state->vrr.cmrr_n)); } intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), @@ -395,7 +394,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) VRR_VSYNC_END(crtc_state->vrr.vsync_end) | VRR_VSYNC_START(crtc_state->vrr.vsync_start)); - if (crtc_state->cmrr.enable) { + if (crtc_state->vrr.mode == INTEL_VRRTG_MODE_CMRR) { intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state)); @@ -437,12 +436,11 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.tg_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; if (HAS_CMRR(display) && trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) { - crtc_state->cmrr.enable = true; crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR; - crtc_state->cmrr.cmrr_n = + crtc_state->vrr.cmrr_n = intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder), TRANS_CMRR_N_HI(display, cpu_transcoder)); - crtc_state->cmrr.cmrr_m = + crtc_state->vrr.cmrr_m = intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder), TRANS_CMRR_M_HI(display, cpu_transcoder)); } else if (trans_vrr_ctl & VRR_CTL_VRR_ENABLE) {