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13 Nov 2024 20:30:58 -0800 X-CSE-ConnectionGUID: bwV2yYl2TAStUUzcSkrRng== X-CSE-MsgGUID: MucWUzJyS++05i59pGcBuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,153,1728975600"; d="scan'208";a="92545752" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa005.fm.intel.com with ESMTP; 13 Nov 2024 20:30:57 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 2/2] drm/i915/watermark: Modify latency programmed into PKG_C_LATENCY Date: Thu, 14 Nov 2024 10:00:41 +0530 Message-Id: <20241114043040.1396947-2-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241114043040.1396947-1-suraj.kandpal@intel.com> References: <20241114043040.1396947-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Increase the latency programmed into PKG_C_LATENCY latency to be a multiple of line time which is written into WM_LINETIME. --v2 -Fix commit subject line [Sai Teja] -Use individual DISPLAY_VER checks instead of range [Sai Teja] -Initialize max_linetime [Sai Teja] --v3 -take into account the scenario when adjusted_latency is 0 [Vinod] --v4 -rename adjusted_latency to latency [Mitul] -fix the condition in which dpkgc is disabled [Vinod] --v5 -Add check to see if max_linetime is 0 [Vinod] WA: 22020299601 Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_wm.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c index 620873d1244f..ce11a69b36cc 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.c +++ b/drivers/gpu/drm/i915/display/intel_wm.c @@ -157,9 +157,10 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc; struct intel_crtc_state *new_crtc_state; - u32 max_latency = LNL_PKG_C_LATENCY_MASK; + u32 latency = LNL_PKG_C_LATENCY_MASK; u32 clear = 0, val = 0; u32 added_waketime = 0; + u32 max_linetime = 0; int i; bool fixed_refresh_rate = false; @@ -171,18 +172,29 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state, new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || !new_crtc_state->vrr.enable) fixed_refresh_rate = true; + + max_linetime = max(new_crtc_state->linetime, max_linetime); } if (fixed_refresh_rate) { - max_latency = skl_watermark_max_latency(i915, 1); - if (max_latency == 0) - max_latency = LNL_PKG_C_LATENCY_MASK; + latency = skl_watermark_max_latency(i915, 1); + + /* Wa_22020299601 */ + if (latency) { + if ((DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) && + max_linetime) + latency = max_linetime * + DIV_ROUND_UP(latency, max_linetime); + } else { + latency = LNL_PKG_C_LATENCY_MASK; + } + added_waketime = DSB_EXE_TIME + display->sagv.block_time_us; } clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; - val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) | + val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency) | REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_waketime); intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val);