diff mbox series

[2/6] drm/i915/wm: Refactor dpkgc value prepration

Message ID 20241115160116.1436521-2-suraj.kandpal@intel.com (mailing list archive)
State New
Headers show
Series [1/6] drm/i915/wm: Initialize max_latency variable to appropriate value | expand

Commit Message

Suraj Kandpal Nov. 15, 2024, 4:01 p.m. UTC 
Refactor the value getting prepped to be written into the PKG_C_LATENCY
register by ORing the REG_FIELD_PREP values instead of having val
getiing operated on twice.
We dont need the clear and val variables to be initialized. Lets also
group all the initialized variable together.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index a49e8915346e..6d5f64ed52ed 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2858,7 +2858,7 @@  static void
 skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc)
 {
 	u32 max_latency = LNL_PKG_C_LATENCY_MASK, added_wake_time = 0;
-	u32 clear = 0, val = 0;
+	u32 clear, val;
 
 	if (DISPLAY_VER(i915) < 20)
 		return;
@@ -2871,9 +2871,9 @@  skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc)
 			i915->display.sagv.block_time_us;
 	}
 
-	clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
-	val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
-	val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
+	clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
+	val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
+		REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
 
 	intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
 }