From patchwork Tue Nov 26 13:27:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uma Shankar X-Patchwork-Id: 13885979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B579FD3B98B for ; Tue, 26 Nov 2024 13:19:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3FEEA10E3FD; Tue, 26 Nov 2024 13:19:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eKKvbHvi"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9B61E10E3FD; Tue, 26 Nov 2024 13:19:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732627192; x=1764163192; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dueB7zJH3XougMdJRpQAlmqGE5QIX/mDIBEFqxe/fss=; b=eKKvbHviyBmlz4iY2vrDMSFUdjxT+FTGwgRoyV9U5CG+45oM+Qw8sh9D OwzkOrT2eZ4Qjcj2MiFFDxfP227XI5SicPJ+ig/xHCt82CurwFDw+dY3P PdcjlmeggXz0I9fzxaSbWXcyhbLwlSLnx0saRs1CaBuplT+S+79CuT/y+ jPdmWdWH/adXmeyaumzIWoRIsGhowFPbk/Sjil96L+GwyGK/jUCkL21sO c79gGdGI/CS9T8rrspsinMokMm/yUuDWXvK5NG4i04FX2cHLJb4wjAUKo eSetH9NiNr7oRjzWNnXuBqC0tbpz5yeeKPgWsqnu+kE2gR2lUkmFvQdn5 A==; X-CSE-ConnectionGUID: mFTelmPnQlqrs8fHhFMrJQ== X-CSE-MsgGUID: CIwyFfLkRZeRhBu+AJNDpA== X-IronPort-AV: E=McAfee;i="6700,10204,11268"; a="44170112" X-IronPort-AV: E=Sophos;i="6.12,186,1728975600"; d="scan'208";a="44170112" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2024 05:19:47 -0800 X-CSE-ConnectionGUID: RueklNUmSzqKV1NElCGbhQ== X-CSE-MsgGUID: +XMgWuhgR+u5ShuqPhW7Tg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,186,1728975600"; d="scan'208";a="114874601" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by fmviesa002.fm.intel.com with ESMTP; 26 Nov 2024 05:19:43 -0800 From: Uma Shankar To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, harry.wentland@amd.com, pekka.paalanen@haloniitty.fi, sebastian.wick@redhat.com, jadahl@redhat.com, mwen@igalia.com, contact@emersion.fr, naveen1.kumar@intel.com, Uma Shankar Subject: [v2 04/25] drm: Add Color lut range attributes Date: Tue, 26 Nov 2024 18:57:09 +0530 Message-ID: <20241126132730.1192571-5-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20241126132730.1192571-1-uma.shankar@intel.com> References: <20241126132730.1192571-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This defines a new structure to define color lut ranges, along with related macro definitions and enums. This will help describe segmented lut ranges/PWL LUTs in the hardware. Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- include/uapi/drm/drm_mode.h | 64 +++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index e5090416c1ae..9ed8b1b1357a 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1175,6 +1175,70 @@ struct hdr_output_metadata { DRM_MODE_PAGE_FLIP_ASYNC | \ DRM_MODE_PAGE_FLIP_TARGET) +/** + * DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE + * + * linearly interpolate between the points + */ +#define DRM_COLOROP_1D_LUT_MULTSEG_INTERPOLATE BIT(0) + +/** + * DRM_COLOROP_1D_LUT_MULTSEG_REUSE_LAST + * + * the last value of the previous range is the + * first value of the current range. + */ +#define DRM_COLOROP_1D_LUT_MULTSEG_REUSE_LAST BIT(1) + +/** + * DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING + * + * the curve must be non-decreasing + */ +#define DRM_COLOROP_1D_LUT_MULTSEG_NON_DECREASING BIT(2) + +/** + * DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE + * + * the curve is reflected across origin for negative inputs + */ +#define DRM_COLOROP_1D_LUT_MULTSEG_REFLECT_NEGATIVE BIT(3) + +/** + * DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL + * + * the same curve (red) is used for blue and green channels as well + */ +#define DRM_COLOROP_1D_LUT_MULTSEG_SINGLE_CHANNEL BIT(4) + +/** + * struct drm_color_lut_range + * + * structure to advertise capability of a color hardware + * block that accepts LUT values. It can represent LUTs with + * varied number of entries and distributions + * (Multi segmented, Logarithmic etc). + */ + +struct drm_color_lut_range { + /* DRM_COLOROP_1D_LUT_MULTSEG_* */ + __u32 flags; + /* number of points on the curve in the segment */ + __u16 count; + /* input start/end values of the segment */ + __s32 start, end; + /* normalization factor. Represents 1.0 in terms of smallest step size */ + __u32 norm_factor; + + /* precision of HW LUT*/ + struct { + /* Integer precision */ + __u16 intp; + /* Fractional precision */ + __u16 fracp; + } precision; +}; + /* * Request a page flip on the specified crtc. *