From patchwork Tue Dec 3 08:47:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Kandpal X-Patchwork-Id: 13891932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30B50E6C61D for ; Tue, 3 Dec 2024 08:47:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B73C510E983; Tue, 3 Dec 2024 08:47:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WO3qjfGB"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2D4F010E978; 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03 Dec 2024 00:47:23 -0800 X-CSE-ConnectionGUID: 7XiX4+L6SLiWFhbF2ILPHQ== X-CSE-MsgGUID: NvGCIKmcRMeX2wwtkLzlrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,204,1728975600"; d="scan'208";a="94198913" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa008.jf.intel.com with ESMTP; 03 Dec 2024 00:47:22 -0800 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: mitulkumar.ajitkumar.golani@intel.com, Suraj Kandpal Subject: [PATCH 5/6] drm/i915/wm: Modify latency programmed into PKG_C_LATENCY Date: Tue, 3 Dec 2024 14:17:05 +0530 Message-Id: <20241203084706.2126189-5-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203084706.2126189-1-suraj.kandpal@intel.com> References: <20241203084706.2126189-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Increase the latency programmed into PKG_C_LATENCY latency to be a multiple of line time which is written into WM_LINETIME. --v2 -Fix commit subject line [Sai Teja] -Use individual DISPLAY_VER checks instead of range [Sai Teja] -Initialize max_linetime [Sai Teja] --v3 -take into account the scenario when adjusted_latency is 0 [Vinod] --v4 -rename adjusted_latency to latency [Mitul] -fix the condition in which dpkgc is disabled [Vinod] --v5 -Add check to see if max_linetime is 0 [Vinod] --v6 -Avoid nested if statements [Mitul] WA: 22020299601 Signed-off-by: Suraj Kandpal Reviewed-by: Mitul Golani --- drivers/gpu/drm/i915/display/skl_watermark.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 95b306c22954..4c032b1758e7 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2861,7 +2861,8 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state) struct drm_i915_private *i915 = to_i915(display->drm); struct intel_crtc *crtc; struct intel_crtc_state *new_crtc_state; - u32 max_latency = LNL_PKG_C_LATENCY_MASK; + u32 latency = LNL_PKG_C_LATENCY_MASK; + u32 max_linetime = 0; u32 clear, val; u32 added_wake_time = 0; bool fixed_refresh_rate = false; @@ -2875,18 +2876,26 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state) (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)) fixed_refresh_rate = true; + + max_linetime = max(new_crtc_state->linetime, max_linetime); } if (fixed_refresh_rate) { - max_latency = skl_watermark_max_latency(i915, 1); - if (max_latency == 0) - max_latency = LNL_PKG_C_LATENCY_MASK; + latency = skl_watermark_max_latency(i915, 1); + /* Wa_22020299601 */ + if ((latency && max_linetime) && + (DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30)) { + latency = max_linetime * DIV_ROUND_UP(latency, max_linetime); + } else if (!latency) { + latency = LNL_PKG_C_LATENCY_MASK; + } + added_wake_time = DSB_EXE_TIME + display->sagv.block_time_us; } clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; - val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) | + val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency) | REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val);