From patchwork Fri Dec 13 06:35:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13906592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BDA0E7717D for ; Fri, 13 Dec 2024 06:35:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB20210EF16; Fri, 13 Dec 2024 06:35:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WgkygZ8M"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8AB5E10EF13; Fri, 13 Dec 2024 06:35:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734071750; x=1765607750; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jMYsJJQFjtLkCBptD6Wd5yxSmG5XsVuFiHd9A4Wgcuw=; b=WgkygZ8MItFHrOmEROwRzktazaG1xt941Kt9RtEpQhvVTPuL/LiY7kk0 NvUbOJhk2sCKTqzKPwkj1moKZMdIXx66Ifrr/LOjGhn+HXs0RYebaNf/h +nRUT4WHmZcBm8o/HOP1Lhf0Woc7GYSplU+ts6TJQ6ZtM+PIx+3YdKKIY MLzw9KjhDps3lD60kzs54sDcuP/RX7WcSmpcncWMgbyNhb7Xg+jYoUlVK VkcBDZT+G7PPMfUVMO8NfzXn7/p1iOC4w6A1YnwgDMFBlyOP8HHdUyzvk upIfEIrcIdllCzgXqXLeHgah9qgfRNA7yB5Y13YkYpF4rbNQA8HLRcC1X Q==; X-CSE-ConnectionGUID: gt5xK6vxRLuDAAjMkyMOOw== X-CSE-MsgGUID: o+2BGcQbREmctLw6z+pbkw== X-IronPort-AV: E=McAfee;i="6700,10204,11284"; a="33846843" X-IronPort-AV: E=Sophos;i="6.12,230,1728975600"; d="scan'208";a="33846843" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 22:35:50 -0800 X-CSE-ConnectionGUID: h26qYFj5RyWtbaNso5IyxA== X-CSE-MsgGUID: Cb6Nh41oQSuFIO6NI7ukgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="96307746" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.191]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 22:35:49 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH 06/10] drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards Date: Fri, 13 Dec 2024 08:35:24 +0200 Message-Id: <20241213063528.2759659-7-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213063528.2759659-1-jouni.hogander@intel.com> References: <20241213063528.2759659-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In LunarLake we have SFF_CTL register which contains SFF bit ored with respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This helps us avoiding taking psr mutex when performing atomic commit. We don't need to set the CFF bit as selective update configuration in PSR2_MAN_TRL_CTL is not overwritten anymore. I.e. we have valid configuration in PSR2_MAN_TRK_CTL and in plane SEL_FETCH_* registers when SFF bit gets cleared by the HW in case something triggers "frame change" event after SFF bit is cleared. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8aa2574ba5c9..bca5ed4f76ba 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2347,7 +2347,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st struct intel_dp *intel_dp = enc_to_intel_dp(encoder); lockdep_assert_held(&intel_dp->psr.lock); - if (intel_dp->psr.psr2_sel_fetch_cff_enabled) + if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) return; break; } @@ -3133,12 +3133,16 @@ static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) drm_crtc_vblank_put(&crtc->base); - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_single_full_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display)); + if (DISPLAY_VER(display) >= 20) + intel_de_write(display, LNL_SFF_CTL(display, cpu_transcoder), + LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); + else + intel_de_write(display, + PSR2_MAN_TRK_CTL(display, cpu_transcoder), + man_trk_ctl_enable_bit_get(display) | + man_trk_ctl_partial_frame_bit_get(display) | + man_trk_ctl_single_full_frame_bit_get(display) | + man_trk_ctl_continuos_full_frame(display)); local_irq_enable(); } @@ -3244,6 +3248,10 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) * Still keep cff bit enabled as we don't have proper SU * configuration in case update is sent for any reason after * sff bit gets cleared by the HW on next vblank. + * + * NOTE: Setting cff bit is not needed for LunarLake onwards as + * we have own register for SFF bit and we are not overwriting + * existing SU configuration */ intel_psr_configure_full_frame_update(intel_dp); }