| Message ID | 20241217063532.2729031-1-nitin.r.gote@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/1] drm/i915/gt: Increase a time to retry RING_HEAD reset | expand |
Hi I915-ci-infra@lists.freedesktop.org, Changes introduced with this patch is not related to the below Possible regression or failure. Please update CBL filters and re-report. Thanks, Nitin
Hi Nitin, ... > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 32f3b52a183a..d56410863f26 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -230,8 +230,13 @@ static int xcs_resume(struct intel_engine_cs *engine) > > set_pp_dir(engine); > > - /* First wake the ring up to an empty/idle ring */ > - for ((kt) = ktime_get() + (2 * NSEC_PER_MSEC); > + /* > + * First wake the ring up to an empty/idle ring. > + * Use 50ms of delay to let the engine write successfully > + * for all platforms. Experimented with different values and I'm going to change /Experimented/Experiments/ Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Thanks, Andi > + * determined that 50ms works best based on testing. > + */ > + for ((kt) = ktime_get() + (50 * NSEC_PER_MSEC); > ktime_before(ktime_get(), (kt)); cpu_relax()) { > /* > * In case of resets fails because engine resumes from > -- > 2.25.1
Hi,
https://patchwork.freedesktop.org/series/142690/- Re-reported.
i915.CI.Full - Re-reported.
Thanks,
Ravali
From: I915-ci-infra <i915-ci-infra-bounces@lists.freedesktop.org> On Behalf Of Gote, Nitin R
Sent: 17 December 2024 16:59
To: i915-ci-infra@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ i915.CI.Full: failure for series starting with [v2,1/1] drm/i915/gt: Increase a time to retry RING_HEAD reset
Hi I915-ci-infra@lists.freedesktop.org<mailto:I915-ci-infra@lists.freedesktop.org>,
Changes introduced with this patch is not related to the below Possible regression or failure.
Please update CBL filters and re-report.
Thanks,
Nitin
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 32f3b52a183a..d56410863f26 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -230,8 +230,13 @@ static int xcs_resume(struct intel_engine_cs *engine) set_pp_dir(engine); - /* First wake the ring up to an empty/idle ring */ - for ((kt) = ktime_get() + (2 * NSEC_PER_MSEC); + /* + * First wake the ring up to an empty/idle ring. + * Use 50ms of delay to let the engine write successfully + * for all platforms. Experimented with different values and + * determined that 50ms works best based on testing. + */ + for ((kt) = ktime_get() + (50 * NSEC_PER_MSEC); ktime_before(ktime_get(), (kt)); cpu_relax()) { /* * In case of resets fails because engine resumes from
Issue seen again where engine resets fails because the engine resumes from an incorrect RING_HEAD. HEAD is still not 0 even after writing into it. This seems to be timing issue and we experimented different values from 5ms to 50ms and found out that 50ms works best based on testing. So, if write doesn't succeed at first then retry again. v2: add a comment (Andi Shyti) Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12806 Signed-off-by: Nitin Gote <nitin.r.gote@intel.com> --- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)