From patchwork Fri Jan 3 17:41:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13925756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED133E7719B for ; Fri, 3 Jan 2025 17:42:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B19BC10E910; Fri, 3 Jan 2025 17:42:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ayzMU5OE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id F32CB10E90F; Fri, 3 Jan 2025 17:42:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1735926161; x=1767462161; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=rc3aGVf6TmPzLbAaL8CYavMq8x3Ye3LC26YYFx0w0ss=; b=ayzMU5OEB/EcjbsUlgia3ktyUM5N+yiipklHYERoMkwhTEBrw+sQWaZs UxwczSsDuNH5JLeISmFpX5/cdlA/jU2ktY+BgYPeQUJYDElj46rW+tBdO H9f55BFzXKv34HGvqXar6zyKLr0uf7S5hdsL8/prDpVnYcndMZfq28OMY R4ztOgNkcKUZDzr79bcopQEgMZ3KrqdHTZIGb7szSPa5Tybe0Rb4iKaGf EJZgqcghHu8JKlk09eo2+YPCaMa7AzJmIpAkDa+F1wuThMPm9SVK8BUDJ 5SaOFubFrWZdAAfsZX7jp/FikoxCe1urb4xKVQh37EoqK9HUeJYNM3Hyk w==; X-CSE-ConnectionGUID: DwpIFzLGTkeOntvuhxtgsQ== X-CSE-MsgGUID: LzKbBepzQl+hZwFQ2EsFQA== X-IronPort-AV: E=McAfee;i="6700,10204,11304"; a="36326351" X-IronPort-AV: E=Sophos;i="6.12,286,1728975600"; d="scan'208";a="36326351" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2025 09:42:41 -0800 X-CSE-ConnectionGUID: QIe5bvDKS3uUtKTEIZLlOw== X-CSE-MsgGUID: Bo0IJBhsT3Wt4kfcp+CSpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="102709617" Received: from inaky-mobl1.amr.corp.intel.com (HELO gjsousa-mobl2.corp.amr.intel.com) ([10.125.110.11]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2025 09:42:39 -0800 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH 3/3] drm/i915/dmc_wl: Track pipe interrupt registers Date: Fri, 3 Jan 2025 14:41:37 -0300 Message-ID: <20250103174223.58140-4-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250103174223.58140-1-gustavo.sousa@intel.com> References: <20250103174223.58140-1-gustavo.sousa@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Pipe interrupt registers live in their respective pipes' power wells, which are below PG0. That means that they must also be tracked as registers that are powered-off during dynamic DC states. There are probably more ranges that we need to track down and add to the powered_off_ranges. However, let's make this change only about pipe interrupt registers to fix some vblank timeouts observed due to the DMC wakelock not being taken for those registers. In the future, we might want to replace powered_off_ranges with a new table to represent registers in PG0, which should be probably easier to maintain. Any register not belonging to that table should be considered powered off during dynamic DC states and, as such, requiring the DMC wakelock for access. Bspec: 72519, 71583 Signed-off-by: Gustavo Sousa Reviewed-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 02de3ae15074..985aa968692e 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -56,6 +56,7 @@ struct intel_dmc_wl_range { }; static const struct intel_dmc_wl_range powered_off_ranges[] = { + { .start = 0x44400, .end = 0x4447f }, /* PIPE interrupt registers */ { .start = 0x60000, .end = 0x7ffff }, {}, };