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[1/3] drm/i915: Increase the timeout of the spinners

Message ID 20250108141318.63823-2-rodrigo.vivi@intel.com (mailing list archive)
State New
Headers show
Series Enable GuC SLPC default balancing strategies v2 | expand

Commit Message

Rodrigo Vivi Jan. 8, 2025, 2:13 p.m. UTC 
Although in most of the cases it will be a lot faster, there are some
rare cases in a few platforms where this can result in a timeout,
specially when we enable the GPU-CPU balancing in GuC SLPC.
The wait by itself consumes CPU and the GPU workload is small enough,
so the priority is given to the CPU and we can expect some delays
here. This number was a random picked number when reducing
it on commit d4b02a4c613e ("drm/i915/selftests: Trim execlists
runtime") in preparation for some scheduler improvements.
Let's move it back up.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/selftests/igt_spinner.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 8c3e1f20e5a1..bb757b922ad9 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -260,5 +260,5 @@  bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq)
 			     100) &&
 		 wait_for(i915_seqno_passed(hws_seqno(spin, rq),
 					    rq->fence.seqno),
-			  50));
+			  1000));
 }