From patchwork Thu Jan 9 07:31:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13932160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56549E7719B for ; Thu, 9 Jan 2025 07:32:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E12F810ED16; Thu, 9 Jan 2025 07:32:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cc1DEUtY"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0AC9210ED13; Thu, 9 Jan 2025 07:32:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736407933; x=1767943933; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=80MINAGWLC0tBQUuNJncqoEQe3+fTTWNG/fd7/QT0N0=; b=cc1DEUtYyoNbK2SGejZayJU/NpooVwOh2ppKAY6+j2lHpXfsq59Y7VFM GJGtyY3TRy4YWBUgqzidu8HpfHqpNQnoPkMChjRZz/YXZT6hjC5YMaZHu CI/6hwRpp3Y+Ea49Qe4dTcAWDLKootF2oTr15aPVvc+Fm/PLmX9p35Fd5 WoC82/xw7YVhhrZm60rp4UXVqmLnC73otCx56OXj20khSJip3RNajgAfj VI5MuncfnMQTv/UPXYLYni1/JiPCxmp7zCqvTGP9BsSH1OI7NOCwODIRh XAdEB6JfTro6GCI5FnydZgnpWCaNZ2t2RV/e69pp8h3C6UKnBaBfV/rGy A==; X-CSE-ConnectionGUID: RkiQhKCtS7OXzgBVGv2hnQ== X-CSE-MsgGUID: e2GOzZESSrCLXLZJYsfFTg== X-IronPort-AV: E=McAfee;i="6700,10204,11309"; a="54200575" X-IronPort-AV: E=Sophos;i="6.12,300,1728975600"; d="scan'208";a="54200575" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 23:32:13 -0800 X-CSE-ConnectionGUID: L0s5sGU/QgeqcMvVieYTuQ== X-CSE-MsgGUID: EbrhMVBiSKeD98QZBcM1+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,300,1728975600"; d="scan'208";a="103297881" Received: from fpallare-mobl4.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.185]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2025 23:32:12 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v3 10/10] drm/i915/psr: Allow DSB usage when PSR is enabled Date: Thu, 9 Jan 2025 09:31:37 +0200 Message-ID: <20250109073137.1977494-11-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250109073137.1977494-1-jouni.hogander@intel.com> References: <20250109073137.1977494-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB usage also when PSR is enabled for LunarLake onwards. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e448ff64660a..58575800fad2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7631,6 +7631,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct intel_display *display = to_intel_display(crtc); if (!new_crtc_state->hw.active) return; @@ -7643,7 +7644,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state->update_planes && !new_crtc_state->vrr.enable && !new_crtc_state->do_async_flip && - !new_crtc_state->has_psr && + (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && !new_crtc_state->scaler_state.scaler_users && !old_crtc_state->scaler_state.scaler_users && !intel_crtc_needs_modeset(new_crtc_state) &&