From patchwork Fri Jan 10 00:28:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 13933347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62238E7719A for ; Fri, 10 Jan 2025 00:29:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D081910E388; Fri, 10 Jan 2025 00:29:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MMQciK2O"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1259D10E388 for ; Fri, 10 Jan 2025 00:29:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736468943; x=1768004943; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=dyJNYxj5yWEzgi5KE6cVrGyu6K/pJOBLPk2w/MWYZgE=; b=MMQciK2OgYDLkbobGBUrYhQbhGlGmKJnRmE4bfNCrEiZgKbF6d/lwbNI urZ5YXtnxkRuZ5qCua+WDtpKe5ghS5S4hCIMzEyWdUjepUniMR5tcXB1z pOtSncPkkW32eqk8NrQ/RUYro6gqJ0eenl5/THazHy3dfgMDloI5wGB3I vJRh9iAcz2u5nIKLafueH+yWqQdStKFVvcuaYeMfJDV7N1W8sqREQhfwG YM/3P5zflDoRyriv7EGuLxiCO9WX+394DT/sNRpOcDr57hYlNhzTNRBxo uH7PM4jc/R6MsFqakcYOFlNA3tTGS/AxgFtKoocybNosLgUkCPXtJVUfD A==; X-CSE-ConnectionGUID: /vc8oEGCSmCjaW+U/1YwNQ== X-CSE-MsgGUID: YgoubpxPTn6GLKZWozUN2g== X-IronPort-AV: E=McAfee;i="6700,10204,11310"; a="39576179" X-IronPort-AV: E=Sophos;i="6.12,302,1728975600"; d="scan'208";a="39576179" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 16:29:01 -0800 X-CSE-ConnectionGUID: 9bAq14S5QPiskpyd+gvCMw== X-CSE-MsgGUID: EkCSZEFVSA+yoabDCay4Rg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,302,1728975600"; d="scan'208";a="134412726" Received: from valcore-skull-1.fm.intel.com ([10.1.39.17]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 16:29:01 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Cc: Daniele Ceraolo Spurio , John Harrison , Matthew Brost Subject: [PATCH] drm/i915/guc: Debug print LRC state entries only if the context is pinned Date: Thu, 9 Jan 2025 16:28:51 -0800 Message-ID: <20250110002851.3584310-1-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" After the context is unpinned the backing memory can also be unpinned, so any accesses via the lrc_reg_state pointer can end up in unmapped memory. To avoid that, make sure to only access that memory if the context is pinned when printing its info. Fixes: 28ff6520a34d ("drm/i915/guc: Update GuC debugfs to support new GuC") Signed-off-by: Daniele Ceraolo Spurio Cc: John Harrison Cc: Matthew Brost Reviewed-by: John Harrison --- I believe this should fix issue #13343, but I wasn't able to repro the bug to confirm that it is indeed gone with this change. .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 20 +++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 12f1ba7ca9c1..22a73e2e6340 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -5519,12 +5519,20 @@ static inline void guc_log_context(struct drm_printer *p, { drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id); drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca); - drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n", - ce->ring->head, - ce->lrc_reg_state[CTX_RING_HEAD]); - drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n", - ce->ring->tail, - ce->lrc_reg_state[CTX_RING_TAIL]); + if (intel_context_pin_if_active(ce)) { + drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n", + ce->ring->head, + ce->lrc_reg_state[CTX_RING_HEAD]); + drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n", + ce->ring->tail, + ce->lrc_reg_state[CTX_RING_TAIL]); + intel_context_unpin(ce); + } else { + drm_printf(p, "\t\tLRC Head: Internal %u, Memory not pinned\n", + ce->ring->head); + drm_printf(p, "\t\tLRC Tail: Internal %u, Memory not pinned\n", + ce->ring->tail); + } drm_printf(p, "\t\tContext Pin Count: %u\n", atomic_read(&ce->pin_count)); drm_printf(p, "\t\tGuC ID Ref Count: %u\n",