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09 Jan 2025 22:37:38 -0800 X-CSE-ConnectionGUID: y26FcdxcRNC62AtNk/tq1g== X-CSE-MsgGUID: 97K8lJWUQ2aszV9Jw1dVRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,303,1728975600"; d="scan'208";a="134477992" Received: from nemesa.iind.intel.com ([10.190.239.22]) by orviesa002.jf.intel.com with ESMTP; 09 Jan 2025 22:37:36 -0800 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Nemesa Garg , Naga Venkata Srikanth V Subject: [PATCH 6/6] drm/i915/display: Load the lut values and enable sharpness Date: Fri, 10 Jan 2025 12:02:44 +0530 Message-Id: <20250110063244.1129552-7-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250110063244.1129552-1-nemesa.garg@intel.com> References: <20250110063244.1129552-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Load the lut values during pipe enable. v2: Add the display version check v3: Fix build issue Signed-off-by: Nemesa Garg Reviewed-by: Naga Venkata Srikanth V --- drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++ drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/skl_scaler.c | 14 +++++++++++++- 4 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index c910168602d2..f502530a98af 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -389,6 +389,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); + if (DISPLAY_VER(dev_priv) >= 20) + drm_crtc_create_sharpness_strength_property(&crtc->base); + return 0; fail: diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 67dfd428d85f..0995881aecb8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1881,6 +1881,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_crtc_wait_for_next_vblank(wa_crtc); } } + + if (new_crtc_state->hw.casf_params.strength_changed) + intel_filter_lut_load(crtc, new_crtc_state); } void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) @@ -7182,6 +7185,9 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_vrr_set_transcoder_timings(new_crtc_state); } + if (intel_casf_strength_changed(new_crtc_state, old_crtc_state)) + intel_casf_enable(new_crtc_state); + intel_fbc_update(state, crtc); drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e5d28377bd0b..589596bfd8c3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -940,6 +940,8 @@ struct intel_casf { struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; u8 win_size; bool need_scaler; + bool strength_changed; + u8 strength; }; void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 57396f610c89..01b1cbaae28f 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -8,6 +8,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_fb.h" +#include "intel_casf_regs.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -875,7 +876,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) /* find scaler attached to this pipe */ for (i = 0; i < crtc->num_scalers; i++) { - u32 ctl, pos, size; + u32 ctl, pos, size, sharp; ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i)); if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE)) @@ -883,6 +884,17 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) id = i; + if (DISPLAY_VER(display) >= 20) { + sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe)); + if (sharp & FILTER_EN) { + crtc_state->hw.casf_params.strength = + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) - 16; + crtc_state->hw.casf_params.need_scaler = true; + crtc_state->hw.casf_params.win_size = + REG_FIELD_GET(FILTER_SIZE_MASK, sharp); + } + } + if (!crtc_state->hw.casf_params.need_scaler) crtc_state->pch_pfit.enabled = true;