| Message ID | 20250115151714.3665211-7-mitulkumar.ajitkumar.golani@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Check Scaler and DSC Prefill Latency Against Vblank | expand |
On 1/15/2025 8:47 PM, Mitul Golani wrote: > High refresh rate panels which may have small line times > and vblank sizes, Check if vblank size is sufficient for > enabled scaler users. > > Bspec: 70151 > > --v2: > - Use hweight* family of functions for counting bits. [Jani] > - Update precision handling for hscale and vscale. [Ankit] > - Consider chroma downscaling factor during latency > calculation. [Ankit] > - Replace function name from scaler_prefill_time to > scaler_prefill_latency. > > --v3: > - hscale_k and vscale_k values are already left shifted > by 16, after multiplying by 1000, those need to be right > shifted to 16. [Ankit] > - Replace YCBCR444 to YCBCR420. [Ankit] > - Divide by 1000 * 1000 in end to get correct precision. [Ankit] > - Initialise latency to 0 to avoid any garbage. > > --v4: > - Elaborate commit message and add Bspec number. [Ankit] > - Improvise latency calculation. [Ankit] > - Use ceiling value for down scaling factor when less than 1 > as per bspec. [Ankit] > - Correct linetime calculation. [Ankit] > - Consider cdclk prefill adjustment while prefill > computation.[Ankit] > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 49 ++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c > index f4458d1185b3..ca9d5677c356 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -2292,6 +2292,54 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, > return 0; > } > > +static int > +cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_atomic_state *state = > + to_intel_atomic_state(crtc_state->uapi.state); > + const struct intel_cdclk_state *cdclk_state; > + > + cdclk_state = intel_atomic_get_cdclk_state(state); > + if (IS_ERR(cdclk_state)) > + return PTR_ERR(cdclk_state); > + > + return min(1, DIV_ROUND_UP(crtc_state->pixel_rate, > + 2 * cdclk_state->logical.cdclk)); I am not sure about this, perhaps need to use : intel_crtc_compute_min_cdclk(). > +} > + > +static int > +scaler_prefill_latency(const struct intel_crtc_state *crtc_state) > +{ > + const struct intel_crtc_scaler_state *scaler_state = > + &crtc_state->scaler_state; > + int num_scaler_users = hweight32(scaler_state->scaler_users); > + int latency = 0; > + int linetime = > + intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, > + DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, > + crtc_state->pixel_rate)); > + long long hscale_k, vscale_k; u64 will be more appropriate. > + > + if (!num_scaler_users) > + return latency; > + > + latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 4 * linetime); > + > + if (num_scaler_users > 1) { > + int chroma_downscaling_factor = > + crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; > + hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); > + vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); > + > + latency += chroma_downscaling_factor * > + DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k), > + 1000000); > + latency *= cdclk_prefill_adjustment(crtc_state); > + } > + > + return latency; If only 1 scaler, cdclk_prefill_adjustment is missing. Regards, Ankit > +} > + > static bool > skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, > int wm0_lines, int latency) > @@ -2302,6 +2350,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, > /* FIXME missing scaler and DSC pre-fill time */ > return crtc_state->framestart_delay + > intel_usecs_to_scanlines(adjusted_mode, latency) + > + scaler_prefill_latency(crtc_state) + > wm0_lines > > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; > }
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index f4458d1185b3..ca9d5677c356 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2292,6 +2292,54 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, return 0; } +static int +cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) +{ + struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->uapi.state); + const struct intel_cdclk_state *cdclk_state; + + cdclk_state = intel_atomic_get_cdclk_state(state); + if (IS_ERR(cdclk_state)) + return PTR_ERR(cdclk_state); + + return min(1, DIV_ROUND_UP(crtc_state->pixel_rate, + 2 * cdclk_state->logical.cdclk)); +} + +static int +scaler_prefill_latency(const struct intel_crtc_state *crtc_state) +{ + const struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + int num_scaler_users = hweight32(scaler_state->scaler_users); + int latency = 0; + int linetime = + intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, + DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, + crtc_state->pixel_rate)); + long long hscale_k, vscale_k; + + if (!num_scaler_users) + return latency; + + latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 4 * linetime); + + if (num_scaler_users > 1) { + int chroma_downscaling_factor = + crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; + hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); + vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); + + latency += chroma_downscaling_factor * + DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k), + 1000000); + latency *= cdclk_prefill_adjustment(crtc_state); + } + + return latency; +} + static bool skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, int wm0_lines, int latency) @@ -2302,6 +2350,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, /* FIXME missing scaler and DSC pre-fill time */ return crtc_state->framestart_delay + intel_usecs_to_scanlines(adjusted_mode, latency) + + scaler_prefill_latency(crtc_state) + wm0_lines > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; }
High refresh rate panels which may have small line times and vblank sizes, Check if vblank size is sufficient for enabled scaler users. Bspec: 70151 --v2: - Use hweight* family of functions for counting bits. [Jani] - Update precision handling for hscale and vscale. [Ankit] - Consider chroma downscaling factor during latency calculation. [Ankit] - Replace function name from scaler_prefill_time to scaler_prefill_latency. --v3: - hscale_k and vscale_k values are already left shifted by 16, after multiplying by 1000, those need to be right shifted to 16. [Ankit] - Replace YCBCR444 to YCBCR420. [Ankit] - Divide by 1000 * 1000 in end to get correct precision. [Ankit] - Initialise latency to 0 to avoid any garbage. --v4: - Elaborate commit message and add Bspec number. [Ankit] - Improvise latency calculation. [Ankit] - Use ceiling value for down scaling factor when less than 1 as per bspec. [Ankit] - Correct linetime calculation. [Ankit] - Consider cdclk prefill adjustment while prefill computation.[Ankit] Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- drivers/gpu/drm/i915/display/skl_watermark.c | 49 ++++++++++++++++++++ 1 file changed, 49 insertions(+)