| Message ID | 20250115230859.2410966-1-clinton.a.taylor@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/display: HDMI C10 PLL entry for 265250 MHz | expand |
Thank You for the patch Without this patch on monitors that support this mode like Acer x34 and LG 34GS95QE. this resolution is rejected as follow: [drm:drm_mode_prune_invalid] Rejected mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443 1453 1474 0x48 0x9 (CLOCK_RANGE) With this patch, we are able to drive this resolution and pixel clock: pipe mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443 1453 1474 0x40 0x9 Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> On Wed, 2025-01-15 at 15:08 -0800, Clint Taylor wrote: > Add PLL values for 265.250MHz pixel clock to support recent 3440x1440 > monitors. > > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index e768dc6a15b3..c5ea8202a455 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -1620,6 +1620,16 @@ static const struct intel_c10pll_state > mtl_c10_hdmi_262750 = { > .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] > = 0x84, .pll[19] = 0x23, > }; > > +static const struct intel_c10pll_state mtl_c10_hdmi_265250 = { > + .clock = 265250, > + .tx = 0x10, > + .cmn = 0x1, > + .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = > 0x00, .pll[4] = 0x00, > + .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = > 0x20, .pll[9] = 0xFF, > + .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x13, .pll[13] > = 0x55, .pll[14] = 0x55, > + .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x0F, .pll[18] > = 0x85, .pll[19] = 0x23, > +}; > + > static const struct intel_c10pll_state mtl_c10_hdmi_268500 = { > .clock = 268500, > .tx = 0x10, > @@ -1728,6 +1738,7 @@ static const struct intel_c10pll_state * const > mtl_c10_hdmi_tables[] = { > &mtl_c10_hdmi_209800, > &mtl_c10_hdmi_241500, > &mtl_c10_hdmi_262750, > + &mtl_c10_hdmi_265250, > &mtl_c10_hdmi_268500, > &mtl_c10_hdmi_296703, > &mtl_c10_hdmi_297000,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index e768dc6a15b3..c5ea8202a455 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -1620,6 +1620,16 @@ static const struct intel_c10pll_state mtl_c10_hdmi_262750 = { .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, }; +static const struct intel_c10pll_state mtl_c10_hdmi_265250 = { + .clock = 265250, + .tx = 0x10, + .cmn = 0x1, + .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00, + .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, + .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x13, .pll[13] = 0x55, .pll[14] = 0x55, + .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x0F, .pll[18] = 0x85, .pll[19] = 0x23, +}; + static const struct intel_c10pll_state mtl_c10_hdmi_268500 = { .clock = 268500, .tx = 0x10, @@ -1728,6 +1738,7 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = { &mtl_c10_hdmi_209800, &mtl_c10_hdmi_241500, &mtl_c10_hdmi_262750, + &mtl_c10_hdmi_265250, &mtl_c10_hdmi_268500, &mtl_c10_hdmi_296703, &mtl_c10_hdmi_297000,
Add PLL values for 265.250MHz pixel clock to support recent 3440x1440 monitors. Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++++++++ 1 file changed, 11 insertions(+)