diff mbox series

[1/8] drm/i915: Keep TRANS_VBLANK.vblank_start==0 on ADL+ even when doing LRR updates

Message ID 20250116201637.22486-2-ville.syrjala@linux.intel.com (mailing list archive)
State New
Headers show
Series drm/i915: Handle vblank delay vs. fastboot and finish DSB plane update enabling | expand

Commit Message

Ville Syrjala Jan. 16, 2025, 8:16 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_set_transcoder_timings() will set TRANS_VBLANK.vblank_start to 0
for clarity on ADL+ (non-DSI) because the hardware no longer uses that
value. So the same in intel_set_transcoder_timings_lrr() to make sure
the registers stay constitent even when doing LRR timing updates.

Cc: Paz Zcharya <pazz@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f5d2eacce119..5ba3b2d658e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2923,6 +2923,14 @@  static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
 
+	if (DISPLAY_VER(dev_priv) >= 13) {
+		/*
+		 * VBLANK_START not used by hw, just clear it
+		 * to make it stand out in register dumps.
+		 */
+		crtc_vblank_start = 1;
+	}
+
 	drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
 
 	/*