| Message ID | 20250120125439.4188626-8-mitulkumar.ajitkumar.golani@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Check Scaler and DSC Prefill Latency Against Vblank | expand |
On 1/20/2025 6:24 PM, Mitul Golani wrote: > High refresh rate panels which may have small line times > and vblank sizes, Check if vblank size is sufficient for > dsc prefill latency. > > --v2: > - Consider chroma downscaling factor in latency calculation. [Ankit] > - Replace with appropriate function name. > > --v3: > - Remove FIXME tag.[Ankit] > - Replace Ycbcr444 to Ycbcr420.[Ankit] > - Correct precision. [Ankit] > - Use some local valiables like linetime_factor and latency to > adjust precision. > - Declare latency to 0 initially to avoid returning any garbage values. > - Account for second scaler downscaling factor as well. [Ankit] > > --v4: > - Improvise hscale and vscale calculation. [Ankit] > - Use appropriate name for number of scaler users. [Ankit] > - Update commit message and rebase. > - Add linetime and cdclk prefill adjustment calculation. [Ankit] > > --v5: > - Update bspec link in trailer. [Ankit] > - Correct hscale, vscale datatype. [Ankit] > - Use intel_crtc_compute_min_cdclk. [Ankit] > > --v6: > - Use cdclk_state->logical.cdclk instead of > intel_crtc_compute_min_cdclk. [Ankit] > > --v7: > - Fix linetime calculation. [Ankit] > - Reduce redandancy use of variables. [Ankit] > - Fix typos. [Ankit] > - Update calculation for precision. [Ankit] > > Bspec: 70151 > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 32 +++++++++++++++++++- > 1 file changed, 31 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c > index 448d320e0d47..89e8da70c333 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -2310,6 +2310,36 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) > 2 * cdclk_state->logical.cdclk)); > } > > +static int > +dsc_prefill_latency(const struct intel_crtc_state *crtc_state) > +{ > + const struct intel_crtc_scaler_state *scaler_state = > + &crtc_state->scaler_state; > + int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, > + crtc_state->hw.adjusted_mode.clock); > + u32 dsc_prefill_latency; Need to initialize this. > + int num_scaler_users = hweight32(scaler_state->scaler_users); > + int chroma_downscaling_factor = > + crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; > + u64 hscale_k, vscale_k; > + These should be local to the loop below. With above fixed: Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > + if (!crtc_state->dsc.compression_enable || !num_scaler_users) > + return dsc_prefill_latency; > + > + dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10); > + > + for (int i = 0; i < num_scaler_users; i++) { > + hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); > + vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); > + dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k, > + 1000000); > + } > + > + dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state); > + > + return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency); > +} > + > static int > scaler_prefill_latency(const struct intel_crtc_state *crtc_state) > { > @@ -2350,10 +2380,10 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, > const struct drm_display_mode *adjusted_mode = > &crtc_state->hw.adjusted_mode; > > - /* FIXME missing DSC pre-fill time */ > return crtc_state->framestart_delay + > intel_usecs_to_scanlines(adjusted_mode, latency) + > scaler_prefill_latency(crtc_state) + > + dsc_prefill_latency(crtc_state) + > wm0_lines > > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; > }
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 448d320e0d47..89e8da70c333 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2310,6 +2310,36 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 2 * cdclk_state->logical.cdclk)); } +static int +dsc_prefill_latency(const struct intel_crtc_state *crtc_state) +{ + const struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, + crtc_state->hw.adjusted_mode.clock); + u32 dsc_prefill_latency; + int num_scaler_users = hweight32(scaler_state->scaler_users); + int chroma_downscaling_factor = + crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; + u64 hscale_k, vscale_k; + + if (!crtc_state->dsc.compression_enable || !num_scaler_users) + return dsc_prefill_latency; + + dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10); + + for (int i = 0; i < num_scaler_users; i++) { + hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); + vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); + dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k, + 1000000); + } + + dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state); + + return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency); +} + static int scaler_prefill_latency(const struct intel_crtc_state *crtc_state) { @@ -2350,10 +2380,10 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - /* FIXME missing DSC pre-fill time */ return crtc_state->framestart_delay + intel_usecs_to_scanlines(adjusted_mode, latency) + scaler_prefill_latency(crtc_state) + + dsc_prefill_latency(crtc_state) + wm0_lines > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; }
High refresh rate panels which may have small line times and vblank sizes, Check if vblank size is sufficient for dsc prefill latency. --v2: - Consider chroma downscaling factor in latency calculation. [Ankit] - Replace with appropriate function name. --v3: - Remove FIXME tag.[Ankit] - Replace Ycbcr444 to Ycbcr420.[Ankit] - Correct precision. [Ankit] - Use some local valiables like linetime_factor and latency to adjust precision. - Declare latency to 0 initially to avoid returning any garbage values. - Account for second scaler downscaling factor as well. [Ankit] --v4: - Improvise hscale and vscale calculation. [Ankit] - Use appropriate name for number of scaler users. [Ankit] - Update commit message and rebase. - Add linetime and cdclk prefill adjustment calculation. [Ankit] --v5: - Update bspec link in trailer. [Ankit] - Correct hscale, vscale datatype. [Ankit] - Use intel_crtc_compute_min_cdclk. [Ankit] --v6: - Use cdclk_state->logical.cdclk instead of intel_crtc_compute_min_cdclk. [Ankit] --v7: - Fix linetime calculation. [Ankit] - Reduce redandancy use of variables. [Ankit] - Fix typos. [Ankit] - Update calculation for precision. [Ankit] Bspec: 70151 Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- drivers/gpu/drm/i915/display/skl_watermark.c | 32 +++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-)