@@ -7685,6 +7685,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_display *display = to_intel_display(crtc);
if (!new_crtc_state->hw.active)
return;
@@ -7726,6 +7727,15 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
state, crtc);
+ /*
+ * Ensure we have "Frame Change" event when PSR state is
+ * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank
+ * evasion hangs as PIPEDSL is reading as 0.
+ */
+ if (new_crtc_state->has_psr && !new_crtc_state->has_panel_replay)
+ intel_de_write_dsb(display, new_crtc_state->dsb_commit,
+ CURSURFLIVE(display, crtc->pipe), 0);
+
intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
if (intel_crtc_needs_color_update(new_crtc_state))
We may have commit which doesn't have any non-arming plane register writes. In that case there aren't "Frame Change" event before DSB vblank evasion which hangs as PIPEDSL register is reading as 0 when PSR state is SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by adding dummy write triggering the "Frame Change" event. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++ 1 file changed, 10 insertions(+)