From patchwork Fri Jan 24 11:39:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13949315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97CC4C02181 for ; Fri, 24 Jan 2025 11:39:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3640D10E88D; Fri, 24 Jan 2025 11:39:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Gn1FjPme"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 642AF10E921; Fri, 24 Jan 2025 11:39:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737718775; x=1769254775; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JbGoeDw7x0Pntr6HFiJkuRzhfeVqN/impzT1otHpZ64=; b=Gn1FjPme+ztfPg923NWxsaFNiiMRp2QKy5rJFgqmID3snsCKZn3oLfWn Ye0qXyfOEP8vSgEsf+Y4YSXWKcNTSYGyuDrBiOonKRtpcBGPHFEUs/rG6 7kyA044pFrGGuBRl67MCOZoBQLJstRhnAVvk0tz3HL7KTgPNOPhX+4pqz UR7vGA6EgCX5G9zTBhAYYu5kPGPeMS8BmIOhBv9Vj3WNLLcRWLM7iOdpd IKGp1eJSds3XujHsQdGL23MONnu/hLtXYPcKn72rDoITVlHT8BcdUZ65w ihoa6HutdTFM+piaNv96jKr/Mq/+HaK9YSAhN7DwVuFm3Go94bhE8ulEJ A==; X-CSE-ConnectionGUID: dLx1NFPESKOcupgKxI0ldw== X-CSE-MsgGUID: mwFdf0cHQm6FRkKShjZ/Yw== X-IronPort-AV: E=McAfee;i="6700,10204,11325"; a="49237784" X-IronPort-AV: E=Sophos;i="6.13,231,1732608000"; d="scan'208";a="49237784" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2025 03:39:35 -0800 X-CSE-ConnectionGUID: QruuaQTdRYayCzPxX2BotQ== X-CSE-MsgGUID: Z7UitAacRfiMQZbfYvBFUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,231,1732608000"; d="scan'208";a="112757834" Received: from smoticic-mobl1.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.245.138]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2025 03:39:32 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Animesh Manna Subject: [PATCH v5 07/13] drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use Date: Fri, 24 Jan 2025 13:39:00 +0200 Message-ID: <20250124113906.850488-8-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250124113906.850488-1-jouni.hogander@intel.com> References: <20250124113906.850488-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Do needed changes to handle PSR2_MAN_TRK_CTL correctly when DSB is in use: 1. Write PSR2_MAN_TRK_CTL in commit_pipe_pre_planes only when not using DSB. 2. Add PSR2_MAN_TRK_CTL writing into DSB commit in intel_atomic_dsb_finish. Taking PSR lock over DSB commit is not needed because PSR2_MAN_TRK_CTL is now written only by DSB. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index aed35f203fd8d..5db2af86d0c8a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7143,7 +7143,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state, intel_pipe_fastset(old_crtc_state, new_crtc_state); } - intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state); + if (!new_crtc_state->use_dsb) + intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state); intel_atomic_update_watermarks(state, crtc); } @@ -7731,6 +7732,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state); bdw_set_pipe_misc(new_crtc_state->dsb_commit, new_crtc_state); + intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit, + new_crtc_state); intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, state, crtc);