| Message ID | 20250124150020.2271747-25-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Use VRR timing generator for fixed refresh rate modes | expand |
On Fri, Jan 24, 2025 at 08:30:09PM +0530, Ankit Nautiyal wrote: > DP sink uses MSA timings for the fixed refresh rate mode. > For using VRR timing generator for fixed refresh rate mode, the HW prepares > the Vtotal for the MSA from the VMAX register. Since the MSA Vtotal is > one-based while Vmax is zero-based we need to take care of this while > setting Vtotal value for the fixed refresh rate mode. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index f485c3e35d68..5a1b0d61c483 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -264,6 +264,18 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, int vmin > crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > } > > +static > +int adjust_vtotal_for_msa(int vtotal) > +{ > + /* > + * DP sink uses MSA timings for the fixed refresh rate mode. > + * The HW prepares the Vtotal for the MSA from the VMAX register. > + * Since the MSA Vtotal is one-based while Vmax is zero-based we need to > + * take care of this while setting Vtotal value. Hang on. If the hardware is broken enough that it forgets to put the +1 into MSA then that means we should be increasing vmax if we want the proper number to appear there. But that would actually just increase the length of the frame and the MSA would still be off by one. > + */ > + return vtotal - 1; > +} > + > static > int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) > { > @@ -274,7 +286,7 @@ int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) > * For this set the vmin as crtc_vtotal. With this we never need to > * change anything to do with the guardband. > */ > - return crtc_state->hw.adjusted_mode.crtc_vtotal; > + return adjust_vtotal_for_msa(crtc_state->hw.adjusted_mode.crtc_vtotal); > } > > static > -- > 2.45.2
On 1/25/2025 2:31 AM, Ville Syrjälä wrote: > On Fri, Jan 24, 2025 at 08:30:09PM +0530, Ankit Nautiyal wrote: >> DP sink uses MSA timings for the fixed refresh rate mode. >> For using VRR timing generator for fixed refresh rate mode, the HW prepares >> the Vtotal for the MSA from the VMAX register. Since the MSA Vtotal is >> one-based while Vmax is zero-based we need to take care of this while >> setting Vtotal value for the fixed refresh rate mode. >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_vrr.c | 14 +++++++++++++- >> 1 file changed, 13 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c >> index f485c3e35d68..5a1b0d61c483 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c >> @@ -264,6 +264,18 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, int vmin >> crtc_state->mode_flags |= I915_MODE_FLAG_VRR; >> } >> >> +static >> +int adjust_vtotal_for_msa(int vtotal) >> +{ >> + /* >> + * DP sink uses MSA timings for the fixed refresh rate mode. >> + * The HW prepares the Vtotal for the MSA from the VMAX register. >> + * Since the MSA Vtotal is one-based while Vmax is zero-based we need to >> + * take care of this while setting Vtotal value. > Hang on. If the hardware is broken enough that it forgets to put the +1 > into MSA then that means we should be increasing vmax if we want the > proper number to appear there. But that would actually just increase > the length of the frame and the MSA would still be off by one. I was observing blanking on the DP panel, when vmin,vmax,flipline were set to vtotal and MSA_TIMING_PAR_IGNORE_EN set to 0. When I had tested with DP analyser, the MSA seemed to be invalid as the timing taken from VMAX register was 1 more than the required value. After setting VMIN VMAX FLIPLINE with vtotal -1 the issue was no more seen on DP panel. But we are already writing VMAX -1 into the register. I'll check again, if I missed something else and get back on this. Regards, Ankit >> + */ >> + return vtotal - 1; >> +} >> + >> static >> int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) >> { >> @@ -274,7 +286,7 @@ int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) >> * For this set the vmin as crtc_vtotal. With this we never need to >> * change anything to do with the guardband. >> */ >> - return crtc_state->hw.adjusted_mode.crtc_vtotal; >> + return adjust_vtotal_for_msa(crtc_state->hw.adjusted_mode.crtc_vtotal); >> } >> >> static >> -- >> 2.45.2
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index f485c3e35d68..5a1b0d61c483 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -264,6 +264,18 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, int vmin crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } +static +int adjust_vtotal_for_msa(int vtotal) +{ + /* + * DP sink uses MSA timings for the fixed refresh rate mode. + * The HW prepares the Vtotal for the MSA from the VMAX register. + * Since the MSA Vtotal is one-based while Vmax is zero-based we need to + * take care of this while setting Vtotal value. + */ + return vtotal - 1; +} + static int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) { @@ -274,7 +286,7 @@ int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) * For this set the vmin as crtc_vtotal. With this we never need to * change anything to do with the guardband. */ - return crtc_state->hw.adjusted_mode.crtc_vtotal; + return adjust_vtotal_for_msa(crtc_state->hw.adjusted_mode.crtc_vtotal); } static
DP sink uses MSA timings for the fixed refresh rate mode. For using VRR timing generator for fixed refresh rate mode, the HW prepares the Vtotal for the MSA from the VMAX register. Since the MSA Vtotal is one-based while Vmax is zero-based we need to take care of this while setting Vtotal value for the fixed refresh rate mode. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_vrr.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)