diff mbox series

[32/35] drm/i915/vrr: Prepare for Fixed refresh rate mode from MTL+

Message ID 20250124150020.2271747-33-ankit.k.nautiyal@intel.com (mailing list archive)
State New
Headers show
Series Use VRR timing generator for fixed refresh rate modes | expand

Commit Message

Nautiyal, Ankit K Jan. 24, 2025, 3 p.m. UTC 
Add vrr enable/disable steps to the modeset sequence for MTL+ when we
want to always use the vrr timing generator.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_vrr.c     |  5 +++++
 drivers/gpu/drm/i915/display/intel_vrr.h     |  2 ++
 3 files changed, 22 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a0d6360f4cda..6d01c76d17ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1301,6 +1301,7 @@  static void intel_pre_plane_update(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_display * display = to_intel_display(state);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
@@ -1310,8 +1311,12 @@  static void intel_pre_plane_update(struct intel_atomic_state *state,
 	intel_psr_pre_plane_update(state, crtc);
 
 	if (intel_crtc_vrr_disabling(state, crtc)) {
-		intel_vrr_disable(old_crtc_state, false);
-		intel_crtc_update_active_timings(old_crtc_state, false);
+		if (intel_vrr_always_use_vrr_tg(display)) {
+			intel_vrr_disable(old_crtc_state, true);
+		} else {
+			intel_vrr_disable(old_crtc_state, false);
+			intel_crtc_update_active_timings(old_crtc_state, false);
+		}
 	}
 
 	if (audio_disabling(old_crtc_state, new_crtc_state))
@@ -1765,8 +1770,12 @@  static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 	}
 
 	intel_set_transcoder_timings(crtc_state);
-	if (HAS_VRR(dev_priv))
-		intel_vrr_set_transcoder_timings(crtc_state);
+	if (HAS_VRR(dev_priv)) {
+		if (intel_vrr_always_use_vrr_tg(display))
+			intel_vrr_enable(crtc_state, false);
+		else
+			intel_vrr_set_transcoder_timings(crtc_state);
+	}
 
 	if (cpu_transcoder != TRANSCODER_EDP)
 		intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder),
@@ -7149,6 +7158,7 @@  static void commit_pipe_post_planes(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
@@ -7162,7 +7172,7 @@  static void commit_pipe_post_planes(struct intel_atomic_state *state,
 		skl_detach_scalers(new_crtc_state);
 
 	if (intel_crtc_vrr_enabling(state, crtc))
-		intel_vrr_enable(new_crtc_state, false);
+		intel_vrr_enable(new_crtc_state, intel_vrr_always_use_vrr_tg(display));
 }
 
 static void intel_enable_crtc(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 10a9bcb8daae..5d0db6277715 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -321,6 +321,11 @@  bool intel_vrrtg_is_enabled(const struct intel_crtc_state *crtc_state)
 	return crtc_state->vrr.mode == INTEL_VRRTG_MODE_VRR;
 }
 
+bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
+{
+	return DISPLAY_VER(display) >= 14;
+}
+
 void
 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			 struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index da6a86cee0e8..489acd64010c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -13,6 +13,7 @@  struct intel_atomic_state;
 struct intel_connector;
 struct intel_crtc_state;
 struct intel_dsb;
+struct intel_display;
 
 bool intel_vrr_is_capable(struct intel_connector *connector);
 bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh);
@@ -34,5 +35,6 @@  int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state);
 bool intel_vrrtg_is_enabled(const struct intel_crtc_state *crtc_state);
+bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 
 #endif /* __INTEL_VRR_H__ */