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[01/12] drm/i915: Bump RING_FAULT engine ID bits

Message ID 20250211231941.22769-2-ville.syrjala@linux.intel.com (mailing list archive)
State New
Headers show
Series drm/i915: some GT register fixes and cleanups | expand

Commit Message

Ville Syrjälä Feb. 11, 2025, 11:19 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The fault engine ID field has been 5 bits since icl. Bump our
define to match. The extra bits were unused before icl so we
should be able to use the larger mask unconditionally.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 6dba65e54cdb..5e4f0545f558 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1041,7 +1041,7 @@ 
 #define GEN12_RING_FAULT_REG			_MMIO(0xcec4)
 #define XEHP_RING_FAULT_REG			MCR_REG(0xcec4)
 #define XELPMP_RING_FAULT_REG			_MMIO(0xcec4)
-#define   GEN8_RING_FAULT_ENGINE_ID(x)		(((x) >> 12) & 0x7)
+#define   GEN8_RING_FAULT_ENGINE_ID(x)		(((x) >> 12) & 0x1f)
 #define   RING_FAULT_GTTSEL_MASK		(1 << 11)
 #define   RING_FAULT_SRCID(x)			(((x) >> 3) & 0xff)
 #define   RING_FAULT_FAULT_TYPE(x)		(((x) >> 1) & 0x3)