diff mbox series

[05/19] drm/i915/vrr: Track vrr.enable only for variable timing

Message ID 20250214121130.1808451-6-ankit.k.nautiyal@intel.com (mailing list archive)
State New
Headers show
Series Use VRR timing generator for fixed refresh rate modes | expand

Commit Message

Nautiyal, Ankit K Feb. 14, 2025, 12:11 p.m. UTC 
Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing
generator is used with variable timings.

Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable
when vmax == vmin == flipline (fixed refresh rate timing).

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

Comments

Ville Syrjälä Feb. 17, 2025, 6:06 p.m. UTC | #1 
On Fri, Feb 14, 2025 at 05:41:15PM +0530, Ankit Nautiyal wrote:
> Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing
> generator is used with variable timings.
> 
> Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable
> when vmax == vmin == flipline (fixed refresh rate timing).
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 0ee7fb0362ce..efa2aa284285 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -226,7 +226,6 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
>  static
>  void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
>  {
> -	crtc_state->vrr.enable = true;
>  	crtc_state->cmrr.enable = true;
>  	/*
>  	 * TODO: Compute precise target refresh rate to determine
> @@ -528,6 +527,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>  	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
>  }
>  
> +static
> +bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
> +{
> +	return crtc_state->vrr.flipline &&
> +	       crtc_state->vrr.flipline == crtc_state->vrr.vmax &&
> +	       crtc_state->vrr.flipline == crtc_state->vrr.vmin;

crtc_state->vrr.flipling == intel_vrr_vmin_flipline(...)
to make this also do the right thing for icl/tgl.

> +}
> +
>  void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> @@ -537,7 +544,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  	trans_vrr_ctl = intel_de_read(display,
>  				      TRANS_VRR_CTL(display, cpu_transcoder));
>  
> -	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
>  	if (HAS_CMRR(display))
>  		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
>  
> @@ -577,6 +583,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>  		}
>  	}
>  
> +	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE &&
> +				 !intel_vrr_is_fixed_rr(crtc_state);
> +
>  	if (crtc_state->vrr.enable)
>  		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>  }
> -- 
> 2.45.2
Nautiyal, Ankit K Feb. 19, 2025, 12:35 p.m. UTC | #2 
On 2/17/2025 11:36 PM, Ville Syrjälä wrote:
> On Fri, Feb 14, 2025 at 05:41:15PM +0530, Ankit Nautiyal wrote:
>> Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing
>> generator is used with variable timings.
>>
>> Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable
>> when vmax == vmin == flipline (fixed refresh rate timing).
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++--
>>   1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 0ee7fb0362ce..efa2aa284285 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -226,7 +226,6 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
>>   static
>>   void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
>>   {
>> -	crtc_state->vrr.enable = true;
>>   	crtc_state->cmrr.enable = true;
>>   	/*
>>   	 * TODO: Compute precise target refresh rate to determine
>> @@ -528,6 +527,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>>   	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
>>   }
>>   
>> +static
>> +bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
>> +{
>> +	return crtc_state->vrr.flipline &&
>> +	       crtc_state->vrr.flipline == crtc_state->vrr.vmax &&
>> +	       crtc_state->vrr.flipline == crtc_state->vrr.vmin;
> crtc_state->vrr.flipling == intel_vrr_vmin_flipline(...)
> to make this also do the right thing for icl/tgl.

Sure, will make the suggested changes.

Regards,

Ankit

>
>> +}
>> +
>>   void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>> @@ -537,7 +544,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   	trans_vrr_ctl = intel_de_read(display,
>>   				      TRANS_VRR_CTL(display, cpu_transcoder));
>>   
>> -	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
>>   	if (HAS_CMRR(display))
>>   		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
>>   
>> @@ -577,6 +583,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   		}
>>   	}
>>   
>> +	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE &&
>> +				 !intel_vrr_is_fixed_rr(crtc_state);
>> +
>>   	if (crtc_state->vrr.enable)
>>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>   }
>> -- 
>> 2.45.2
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 0ee7fb0362ce..efa2aa284285 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -226,7 +226,6 @@  cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
 static
 void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 {
-	crtc_state->vrr.enable = true;
 	crtc_state->cmrr.enable = true;
 	/*
 	 * TODO: Compute precise target refresh rate to determine
@@ -528,6 +527,14 @@  void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
 }
 
+static
+bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->vrr.flipline &&
+	       crtc_state->vrr.flipline == crtc_state->vrr.vmax &&
+	       crtc_state->vrr.flipline == crtc_state->vrr.vmin;
+}
+
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -537,7 +544,6 @@  void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	trans_vrr_ctl = intel_de_read(display,
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
-	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
 	if (HAS_CMRR(display))
 		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
 
@@ -577,6 +583,9 @@  void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 		}
 	}
 
+	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE &&
+				 !intel_vrr_is_fixed_rr(crtc_state);
+
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }