From patchwork Mon Mar 3 08:35:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13998389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83AD8C282D0 for ; Mon, 3 Mar 2025 08:57:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CBF7310E38E; Mon, 3 Mar 2025 08:57:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DTQcQGq5"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8433210E38D; Mon, 3 Mar 2025 08:57:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740992257; x=1772528257; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HiLsySNHqUZiEptD+yvHhNZflLkVyAyH9coRD9NcqJs=; b=DTQcQGq5qH2tCjNj9G2ph2CCx5Y3/B80OIcls++UyyKUVJbR89Ih4REN GP3+Mlqa3dw8SGnEFaQ2VQWp70gPG37e6VzfNcmltqx5Cd0GCNjYQ8FRv IFgDca2iQyx6IKvoSsEA2Z4dzb/3NTLopIIEyebmsUMxOlM37v1G1sdTr AbQz4gfaRKp7hKeeILiFU/wkO4nzUlDYU59rBCHrP35iz3rH9lkv5Dde6 gncEDGqVyP8YNrcYygset1NXG6fSkyXF/w9LQKuijC+dI+OityUV7asJc v8MG5hSmsHF8SGnDkivFyjdyoM3ivUFDSDgpOV2jv30R0Q46Q7Xr1a/2J w==; X-CSE-ConnectionGUID: TYQIjJdTTtaMU7BOuzN9uw== X-CSE-MsgGUID: XOe9HFvZSiCGVFNerhPHXw== X-IronPort-AV: E=McAfee;i="6700,10204,11361"; a="41770028" X-IronPort-AV: E=Sophos;i="6.13,329,1732608000"; d="scan'208";a="41770028" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2025 00:57:36 -0800 X-CSE-ConnectionGUID: JF8JShBvSYyuNkc/sr1HOw== X-CSE-MsgGUID: ahUrkIf/Scedb7tEh0A3ag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,329,1732608000"; d="scan'208";a="117949551" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by fmviesa007.fm.intel.com with ESMTP; 03 Mar 2025 00:57:34 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jouni.hogander@intel.com, jani.nikula@intel.com, jeevan.b@intel.com, Animesh Manna Subject: [PATCH v5 2/8] drm/i915/lobf: Disintegrate alpm_disable from psr_disable Date: Mon, 3 Mar 2025 14:05:16 +0530 Message-Id: <20250303083522.845224-3-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20250303083522.845224-1-animesh.manna@intel.com> References: <20250303083522.845224-1-animesh.manna@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently clearing of alpm registers is done through psr_disable() which is always not correct, without psr also alpm can exist. So dis-integrate alpm_disable() from psr_disable(). v1: Initial version. v2: - Remove h/w register read from alpm_disable(). [Jani] Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_alpm.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_alpm.h | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ .../gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 11 ----------- 5 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 354510bb437d..d2f133bc5f38 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -365,6 +365,7 @@ void intel_alpm_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { lnl_alpm_configure(intel_dp, crtc_state); + intel_dp->alpm_parameters.transcoder = crtc_state->cpu_transcoder; } void intel_alpm_post_plane_update(struct intel_atomic_state *state, @@ -440,3 +441,20 @@ void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_edp_lobf_info", 0444, root, connector, &i915_edp_lobf_info_fops); } + +void intel_alpm_disable(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + enum transcoder cpu_transcoder = intel_dp->alpm_parameters.transcoder; + + if (DISPLAY_VER(display) < 20) + return; + + intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder), + ALPM_CTL_ALPM_ENABLE | ALPM_CTL_LOBF_ENABLE | + ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); + + intel_de_rmw(display, + PORT_ALPM_CTL(cpu_transcoder), + PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); +} diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index 2f862b0476a8..91f51fb24f98 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -28,4 +28,5 @@ void intel_alpm_post_plane_update(struct intel_atomic_state *state, void intel_alpm_lobf_debugfs_add(struct intel_connector *connector); bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp); bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp); +void intel_alpm_disable(struct intel_dp *intel_dp); #endif diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7983ef373d..9b504dcfb446 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -35,6 +35,7 @@ #include "i915_drv.h" #include "i915_reg.h" #include "icl_dsi.h" +#include "intel_alpm.h" #include "intel_audio.h" #include "intel_audio_regs.h" #include "intel_backlight.h" @@ -3569,6 +3570,7 @@ static void intel_ddi_disable_dp(struct intel_atomic_state *state, intel_dp->link_trained = false; intel_psr_disable(intel_dp, old_crtc_state); + intel_alpm_disable(intel_dp); intel_edp_backlight_off(old_conn_state); /* Disable the decompression in DP Sink */ intel_dp_sink_disable_decompression(state, diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4440521e3e9e..b78721c451b8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1801,6 +1801,7 @@ struct intel_dp { struct { u8 io_wake_lines; u8 fast_wake_lines; + enum transcoder transcoder; /* LNL and beyond */ u8 check_entry_lines; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c1dd9c739fd4..1d202f2eb356 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2141,17 +2141,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) if (intel_dp_is_edp(intel_dp)) intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); - /* Panel Replay on eDP is always using ALPM aux less. */ - if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { - intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder), - ALPM_CTL_ALPM_ENABLE | - ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); - - intel_de_rmw(display, - PORT_ALPM_CTL(cpu_transcoder), - PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); - } - /* Disable PSR on Sink */ if (!intel_dp->psr.panel_replay_enabled) { drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);