From patchwork Tue Mar 4 08:19:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6613C282D3 for ; Tue, 4 Mar 2025 08:32:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4519710E522; Tue, 4 Mar 2025 08:32:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CBr2A3hw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id E311410E535; Tue, 4 Mar 2025 08:32:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077140; x=1772613140; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sLcVJYyPe+eQ1EGi3djoLJw21g7jlTfzxUazH19/w04=; b=CBr2A3hwJpOGziNg2wzvEZJNLDKVbPsk/nDGZEI4MD3+ap8Kdu7KZzeh js3sbHy4iERiqEk1O47K8c4M+WVLl1I8lpxSZsiYQ06y4juI8J8EdyWgq G8gwRxNc6XLpjEe/PBidtGDWH7M5XYXf/sO49+ZaeiLRgWiGc8bTtB+2a +tjp8cVHsfmvoj4EmT0+hbmiBi0FXvUJELLWhnd2zotr9AhfGftgUgbd4 nC5eSBIZp8k9cHXu2WXPSFN5kx6yws1OrEVl6ta6ByqCbR3FRuz9xFwHJ 3+dNIA+GDTc4KLk36fipnweTlCrE5DwAI39IkJ/am0evd53Yg3ceBRfRZ g==; X-CSE-ConnectionGUID: bn2iGeS2QqmEQn8g/GzrQQ== X-CSE-MsgGUID: w5pG5xCbSH22UaEXWlXDpQ== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910182" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910182" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:20 -0800 X-CSE-ConnectionGUID: LhlQvrPsSZK3qbc1Njp0lg== X-CSE-MsgGUID: BGLpLl0eRQ+Pm01JE2Frag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492229" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:18 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 12/22] drm/i915/display: Move intel_psr_post_plane_update() at the later Date: Tue, 4 Mar 2025 13:49:38 +0530 Message-ID: <20250304081948.3177034-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In intel_post_plane_update() there are things which might need to do vblank waits, so enabling PSR as early as we do now is simply counter-productive. Therefore move intel_psr_post_plane_update() at the last of intel_post_plane_update(). Signed-off-by: Ankit Nautiyal Suggested-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d1f814050274..a885694df90a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1048,8 +1048,6 @@ static void intel_post_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - intel_psr_post_plane_update(state, crtc); - intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) @@ -1078,6 +1076,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (audio_enabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_enable(state, crtc); + + intel_psr_post_plane_update(state, crtc); } static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,