From patchwork Tue Mar 4 08:19:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14000180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 088E5C282D3 for ; Tue, 4 Mar 2025 08:32:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A6A7210E544; Tue, 4 Mar 2025 08:32:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="C9yD9R0o"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id E862710E542; Tue, 4 Mar 2025 08:32:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741077157; x=1772613157; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BNmWs20YQxQuoqYOoJ0Xw/bPmYJRnYXmYt1z4pkxEzM=; b=C9yD9R0oOALhM2cxK+6uUnZaYHQhjOfdinHt8IXl7gzulDf1FEjFt7y0 IdzvSEKK62Lt8G1DsPMTUvOz1rySiHTdAJb+L/WNQt1gEUoP6532ebAIQ FRgKmjXBmI2wlZIB71y4LSULZDoYI1iMQwHzvc6FjVUA0YO3gggw/phve L5NwCQK57EFixk0tAJLWQIZ8RR9hmDNGCSicgN96N1UWxpNobcLG+Bhc2 4ctedtUwrJfgBq8AKPfrHe551pxwUBJELq/tH0/wpq1rygAWvE0v5hXoB vL9p9ychTgPoeMFaMppDKUCIhqqiJ6kacr12pfn/SEPmCf3IQKLg71N1x g==; X-CSE-ConnectionGUID: /2rx2qHxTnuEmXHanBJzow== X-CSE-MsgGUID: WH2vs0oqQguf9gYDYHiSGQ== X-IronPort-AV: E=McAfee;i="6700,10204,11362"; a="45910208" X-IronPort-AV: E=Sophos;i="6.13,331,1732608000"; d="scan'208";a="45910208" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:37 -0800 X-CSE-ConnectionGUID: 53Yq1gZhQwitZQelkINBCw== X-CSE-MsgGUID: C/HtzeixSZyNx4NiaN+SVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="155492264" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 00:32:35 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 20/22] drm/i915/vrr: Always use VRR timing generator for MTL+ Date: Tue, 4 Mar 2025 13:49:46 +0530 Message-ID: <20250304081948.3177034-21-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> References: <20250304081948.3177034-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently VRR timing generator is used only when VRR is enabled by userspace for sinks that support VRR. From MTL+ gradually move away from the older timing generator and use VRR timing generator for both variable and fixed timings. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vrr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 2b6d022434d2..bb6825c20330 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -560,7 +560,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) if (!HAS_VRR(display)) return false; - /* #TODO return true for platforms supporting fixed_rr */ + if (DISPLAY_VER(display) >= 14) + return true; + return false; }