From patchwork Mon Mar 10 12:16:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 14009871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73BD5C35FF2 for ; Mon, 10 Mar 2025 12:28:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 06C0A10E437; Mon, 10 Mar 2025 12:28:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mA/NL26P"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 408E910E437; Mon, 10 Mar 2025 12:28:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741609717; x=1773145717; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fjRQI7+XyuhqlYNzouiLm9YBnas0Hb1ABgzhKBNhcU4=; b=mA/NL26PumtGV1P2J9+XwPOBR6FZE3Q9PLb+EvD9U0XxMaHnXSY8q28Y CrUFBeL1lo8dwPyFYGvngkmnh/LUPVb48pV1PtneJEZwOmTZCiG83dxjZ lTZmOJF9/M7KzO68xtM6NxwZafV8Zl4C+WHKagh1g+VhdY+12d55Y7gKs Ixdd+Pb6nfh0GqxI+cqMv5zAM1xR0z4FeXT7RR4XeSFUk2ThgtjFj2hgW Wjr3Vh5E8h9PvFCsj6z6/DRoMmjfM0L981BKNZPNTXtm3Bt2o8UfQmLOv mAq5IKR9SSZbig44AgUdHd1lRkfOEpZFifVj0s3DGk9bR348TC9Fb8shg A==; X-CSE-ConnectionGUID: /fAfhI+BQ6qs+6nINYFWNg== X-CSE-MsgGUID: 50uSnRB9TeS97qWJS3OMRA== X-IronPort-AV: E=McAfee;i="6700,10204,11369"; a="65057307" X-IronPort-AV: E=Sophos;i="6.14,236,1736841600"; d="scan'208";a="65057307" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2025 05:28:37 -0700 X-CSE-ConnectionGUID: zQjSrIJqSRO13KvMxY9PQQ== X-CSE-MsgGUID: eOwG1QXMSa2hNThrxwoGnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,236,1736841600"; d="scan'208";a="143180554" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2025 05:28:35 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 12/21] drm/i915/display: Move intel_psr_post_plane_update() at the later Date: Mon, 10 Mar 2025 17:46:06 +0530 Message-ID: <20250310121615.1077079-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250310121615.1077079-1-ankit.k.nautiyal@intel.com> References: <20250310121615.1077079-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In intel_post_plane_update() there are things which might need to do vblank waits, so enabling PSR as early as we do now is simply counter-productive. Therefore move intel_psr_post_plane_update() at the last of intel_post_plane_update(). Signed-off-by: Ankit Nautiyal Suggested-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 246da49af00b..4a0083fdfb05 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1048,8 +1048,6 @@ static void intel_post_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - intel_psr_post_plane_update(state, crtc); - intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) @@ -1078,6 +1076,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (audio_enabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_enable(state, crtc); + + intel_psr_post_plane_update(state, crtc); } static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,