| Message ID | 20250318073540.2773890-5-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Use VRR timing generator for fixed refresh rate modes | expand |
On Tue, Mar 18, 2025 at 01:05:28PM +0530, Ankit Nautiyal wrote: > Currently the variable timings are supported only for DP and eDP and not > for DP MST. Call intel_vrr_compute_config() for MST which will configure > fixed refresh rate timings irrespective of whether VRR is supported or > not. Since vrr_capable still doesn't have support for DP MST this will be > just treated as non VRR case and vrr.vmin/vmax/flipline will be all set > to adjusted_mode->crtc_vtotal. > > This will help to move away from the legacy timing generator and > always use VRR timing generator by default. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 02f95108c637..bd47cf127b4c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -52,6 +52,7 @@ > #include "intel_pfit.h" > #include "intel_psr.h" > #include "intel_vdsc.h" > +#include "intel_vrr.h" > #include "skl_scaler.h" > > /* > @@ -710,6 +711,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, > pipe_config->lane_lat_optim_mask = > bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); > > + intel_vrr_compute_config(pipe_config, conn_state); This looks like it may start to consider MST outputs as VRR capable. Granted we don't attach the uapi property to the conneector so no one can enable actual VRR mode on it, but I think we would enable the LRR codepaths on MST with this. To avoid that I think we want to exclude MST in intel_vrr_is_capable() for now. > + > intel_dp_audio_compute_config(encoder, pipe_config, conn_state); > > intel_ddi_compute_min_voltage_level(pipe_config); > -- > 2.45.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 02f95108c637..bd47cf127b4c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -52,6 +52,7 @@ #include "intel_pfit.h" #include "intel_psr.h" #include "intel_vdsc.h" +#include "intel_vrr.h" #include "skl_scaler.h" /* @@ -710,6 +711,8 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, pipe_config->lane_lat_optim_mask = bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); + intel_vrr_compute_config(pipe_config, conn_state); + intel_dp_audio_compute_config(encoder, pipe_config, conn_state); intel_ddi_compute_min_voltage_level(pipe_config);
Currently the variable timings are supported only for DP and eDP and not for DP MST. Call intel_vrr_compute_config() for MST which will configure fixed refresh rate timings irrespective of whether VRR is supported or not. Since vrr_capable still doesn't have support for DP MST this will be just treated as non VRR case and vrr.vmin/vmax/flipline will be all set to adjusted_mode->crtc_vtotal. This will help to move away from the legacy timing generator and always use VRR timing generator by default. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+)