diff mbox series

drm/i915/display: Add link rate and lane count to i915_display_info

Message ID 20250318220401.3904871-1-khaled.almahallawy@intel.com (mailing list archive)
State New
Headers show
Series drm/i915/display: Add link rate and lane count to i915_display_info | expand

Commit Message

Khaled Almahallawy March 18, 2025, 10:04 p.m. UTC
Adding link rate and lane count information to i915_display_info makes it
easier and faster to access this data compared to checking kernel logs.
This is particularly beneficial for individuals who are not familiar with
i915 in the following scenarios:

* Debugging DP tunnel bandwidth usage in the Thunderbolt driver.
* During USB4 certification, it is necessary to know the link rate used by
  the monitor to prove that the DP tunnel can handle required rates.
* In PHY CTS, when the connector probes are not mounted correctly,
  some display lanes may not appear in the DP Oscilloscope, leading to CTS
  failures.

This change provides validation teams with an easy way to identify and
troubleshoot issues.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Jani Nikula March 24, 2025, 10:55 a.m. UTC | #1
On Tue, 18 Mar 2025, Khaled Almahallawy <khaled.almahallawy@intel.com> wrote:
> Adding link rate and lane count information to i915_display_info makes it
> easier and faster to access this data compared to checking kernel logs.
> This is particularly beneficial for individuals who are not familiar with
> i915 in the following scenarios:
>
> * Debugging DP tunnel bandwidth usage in the Thunderbolt driver.
> * During USB4 certification, it is necessary to know the link rate used by
>   the monitor to prove that the DP tunnel can handle required rates.
> * In PHY CTS, when the connector probes are not mounted correctly,
>   some display lanes may not appear in the DP Oscilloscope, leading to CTS
>   failures.
>
> This change provides validation teams with an easy way to identify and
> troubleshoot issues.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index fdedf65bee53..bda7751472e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -551,9 +551,10 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>  	seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n",
>  		   DRM_MODE_ARG(&crtc_state->hw.pipe_mode));
>  
> -	seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n",
> +	seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d, port_clock=%d, lane_count=%d\n",
>  		   DRM_RECT_ARG(&crtc_state->pipe_src),
> -		   str_yes_no(crtc_state->dither), crtc_state->pipe_bpp);
> +		   str_yes_no(crtc_state->dither), crtc_state->pipe_bpp,
> +		   crtc_state->port_clock, crtc_state->lane_count);

Maybe deserves to be a separate line instead of bundling it with pipe
src etc?

Also, lane_count is bound to be 0 for a lot of outputs where it's
irrelevant.

BR,
Jani.

>  
>  	intel_scaler_info(m, crtc);
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index fdedf65bee53..bda7751472e2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -551,9 +551,10 @@  static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
 	seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&crtc_state->hw.pipe_mode));
 
-	seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n",
+	seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d, port_clock=%d, lane_count=%d\n",
 		   DRM_RECT_ARG(&crtc_state->pipe_src),
-		   str_yes_no(crtc_state->dither), crtc_state->pipe_bpp);
+		   str_yes_no(crtc_state->dither), crtc_state->pipe_bpp,
+		   crtc_state->port_clock, crtc_state->lane_count);
 
 	intel_scaler_info(m, crtc);