From patchwork Mon Mar 24 13:29:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 14027344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33D3AC3600C for ; Mon, 24 Mar 2025 13:31:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C428D10E3FF; Mon, 24 Mar 2025 13:31:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SVX+3UkJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38EB910E405; Mon, 24 Mar 2025 13:31:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742823075; x=1774359075; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ec4keQkax8q652yYyRWcqB084B5FwldDIKKQW0gvYXc=; b=SVX+3UkJHlrsptGyFCv+FR61vXypnb0ZNhI+e0Fq9AfdjCjZpFxg4jYa w4DdZYylE5rwB333BnvlWCFtslha2CVfYOTmjPhTJeSAjPEcnzHdSmaTV TpXLsjlH0k7v+oBpXK+DSvg71guuncRWwQXrJ9Siv0nN9AkFpGmGqIwh7 toy0Ai7dSi5WYmMHDXk4MyG2hqe1Ye3Qt6tCGN61hKcDGfhMGzdGY58+P NjvnZEDTzOnrtfqvwNFeg83cULcBPLvtkuF8Nh0MYqEFFC00DiQZPiggh 2g5P4JsAATiOaNuhPSw6+W9c/5Op5Jve430HJhv/Tas5AH97VzuMwVKSo w==; X-CSE-ConnectionGUID: TVseiJblTHmR/nNZ+aTv7w== X-CSE-MsgGUID: Su1w+tIoQ8GUtZcyt0HuDA== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="55024697" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="55024697" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:31:15 -0700 X-CSE-ConnectionGUID: n9X/B3GjRBqflKxyrwws2A== X-CSE-MsgGUID: L+Orx1lzTcmxFa/AK+6V2A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="155060061" Received: from slindbla-desk.ger.corp.intel.com (HELO localhost) ([10.245.246.252]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:31:11 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Tvrtko Ursulin , Joonas Lahtinen , Chris Wilson , Simona Vetter , Arshad Mehmood , Michal Mrozek , Andi Shyti , Andi Shyti Subject: [PATCH v4 08/15] drm/i915/gt: Remove cslices mask value from the CCS structure Date: Mon, 24 Mar 2025 14:29:44 +0100 Message-ID: <20250324132952.1075209-9-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250324132952.1075209-1-andi.shyti@linux.intel.com> References: <20250324132952.1075209-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Following the decision to manage CCS engine creation within UABI engines, the "cslices" variable in the "ccs" structure in the "gt" is no longer needed. Remove it is now redundant. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 ----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index a6c33b471567..fc8a23fc28b6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -9,7 +9,7 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { - unsigned long cslices_mask = gt->ccs.cslices; + unsigned long cslices_mask = CCS_MASK(gt); u32 mode_val = 0; /* CCS engine id, i.e. the engines position in the engine's bitmask */ int engine; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 9e257f34d05b..71e43071da0b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -218,11 +218,6 @@ struct intel_gt { * i.e. how the CCS streams are distributed amongs the slices. */ struct { - /* - * Mask of the non fused CCS slices - * to be used for the load balancing - */ - intel_engine_mask_t cslices; u32 mode_reg_val; } ccs;