| Message ID | 20250324133248.4071909-15-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Use VRR timing generator for fixed refresh rate modes | expand |
On Mon, Mar 24, 2025 at 07:02:46PM +0530, Ankit Nautiyal wrote: > We now always set vrr.flipline, vmin, and vmax for all platforms that > support VRR. Therefore, we should set all TRANS_VRR_CTL bits except > VRR_ENABLE. Without this, the readback for these bits will fail because we > only read vrr.flipline, vmin, and vmax if TRANS_VRR_CTL has the > FLIPLINE_EN bit set. > > For platforms that always have the VRR Timing Generator enabled, > the FLIPLINE_EN bit is always set in TRANS_VRR_CTL during > intel_transcoder_vrr_enable(). However, for the remaining platforms > (that do not always have the VRR Timing Generator enabled) if a full > modeset doesn't occur and VRR is not enabled, the bit is not set. > > This results in a mismatch between the software state and hardware state > because the software state expects VRR timings like flipline, vmin, and > vmax to be set, but the readout for these doesn't happen since the > FLIPLINE_EN bit is not set in TRANS_VRR_CTL. > > To avoid this mismatch, write trans_vrr_ctl in > intel_vrr_set_transcoder_timings() even when VRR is not enabled > for platforms that do not have the VRR Timing Generator always enabled. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 5e60da2bb0c3..414f93851059 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -484,6 +484,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) > > intel_vrr_set_fixed_rr_timings(crtc_state); > > + if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable) > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), > + trans_vrr_ctl(crtc_state)); > + The whole situation around intel_vrr_set_transcoder_timings() is a bit of a mess now. Technically intel_pre_update_crtc() shouldn't need to call it at all anymore since we set up everything during crtc enable, intel_set_transcoder_timings_lrr() and vrr_enable(). But this fastboot case is somewhat of a special case. I think we probably need to clean this stuff up further. But for the moment this looks fine since VRR should be disabled whenever this is called, and therefore it just does some redundant VRR register writes in the typical case. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > if (HAS_AS_SDP(display)) > intel_de_write(display, > TRANS_VRR_VSYNC(display, cpu_transcoder), > -- > 2.45.2
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5e60da2bb0c3..414f93851059 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -484,6 +484,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) intel_vrr_set_fixed_rr_timings(crtc_state); + if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable) + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), + trans_vrr_ctl(crtc_state)); + if (HAS_AS_SDP(display)) intel_de_write(display, TRANS_VRR_VSYNC(display, cpu_transcoder),
We now always set vrr.flipline, vmin, and vmax for all platforms that support VRR. Therefore, we should set all TRANS_VRR_CTL bits except VRR_ENABLE. Without this, the readback for these bits will fail because we only read vrr.flipline, vmin, and vmax if TRANS_VRR_CTL has the FLIPLINE_EN bit set. For platforms that always have the VRR Timing Generator enabled, the FLIPLINE_EN bit is always set in TRANS_VRR_CTL during intel_transcoder_vrr_enable(). However, for the remaining platforms (that do not always have the VRR Timing Generator enabled) if a full modeset doesn't occur and VRR is not enabled, the bit is not set. This results in a mismatch between the software state and hardware state because the software state expects VRR timings like flipline, vmin, and vmax to be set, but the readout for these doesn't happen since the FLIPLINE_EN bit is not set in TRANS_VRR_CTL. To avoid this mismatch, write trans_vrr_ctl in intel_vrr_set_transcoder_timings() even when VRR is not enabled for platforms that do not have the VRR Timing Generator always enabled. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++ 1 file changed, 4 insertions(+)