[v2,02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/

Message ID	20250326162544.3642-3-ville.syrjala@linux.intel.com (mailing list archive)
State	New
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH v2 02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/ Date: Wed, 26 Mar 2025 18:25:32 +0200 Message-ID: <20250326162544.3642-3-ville.syrjala@linux.intel.com> In-Reply-To: <20250326162544.3642-1-ville.syrjala@linux.intel.com> References: <20250326162544.3642-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: sagv/bw cleanup \| expand [v2,00/14] drm/i915: sagv/bw cleanup [v2,01/14] drm/i915: Drop the cached per-pipe min_cdclk[] from bw state [v2,02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/ [v2,03/14] drm/i915: Extract intel_dbuf_bw_changed() [v2,04/14] drm/i915: Pass intel_dbuf_bw to skl_*_calc_dbuf_bw() explicitly [v2,05/14] drm/i915: Avoid triggering unwanted cdclk changes due to dbuf bandwidth changes [v2,06/14] drm/i915: Do more bw readout [v2,07/14] drm/i915: Flag even inactive crtcs as "inherited" [v2,08/14] drm/i915: Drop force_check_qgv [v2,09/14] drm/i915: Extract intel_bw_modeset_checks() [v2,10/14] drm/i915: Extract intel_bw_check_sagv_mask() [v2,11/14] drm/i915: Make intel_bw_check_sagv_mask() internal to intel_bw.c [v2,12/14] drm/i915: Make intel_bw_modeset_checks() internal to intel_bw_atomic_check() [v2,13/14] drm/i915: Skip bw stuff if per-crtc sagv state doesn't change [v2,14/14] drm/i915: Eliminate intel_compute_sagv_mask()

Message ID

20250326162544.3642-3-ville.syrjala@linux.intel.com (mailing list archive)

State

New

Headers

From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH v2 02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/
Date: Wed, 26 Mar 2025 18:25:32 +0200
Message-ID: <20250326162544.3642-3-ville.syrjala@linux.intel.com>
In-Reply-To: <20250326162544.3642-1-ville.syrjala@linux.intel.com>
References: <20250326162544.3642-1-ville.syrjala@linux.intel.com>
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Series

drm/i915: sagv/bw cleanup | expand

Commit Message

Ville Syrjälä March 26, 2025, 4:25 p.m. UTC

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename the intel_crtc_bw struct to intel_dbuf_bw to better
reflect what it does.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

Comments

Jani Nikula March 27, 2025, 7:57 a.m. UTC | #1

On Wed, 26 Mar 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the intel_crtc_bw struct to intel_dbuf_bw to better
> reflect what it does.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 24 ++++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 15c2377193f7..b34db55f5a7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -1157,15 +1157,15 @@ static bool intel_bw_state_changed(struct intel_display *display,
>  	enum pipe pipe;
>  
>  	for_each_pipe(display, pipe) {
> -		const struct intel_dbuf_bw *old_crtc_bw =
> +		const struct intel_dbuf_bw *old_dbuf_bw =
>  			&old_bw_state->dbuf_bw[pipe];
> -		const struct intel_dbuf_bw *new_crtc_bw =
> +		const struct intel_dbuf_bw *new_dbuf_bw =
>  			&new_bw_state->dbuf_bw[pipe];
>  		enum dbuf_slice slice;
>  
>  		for_each_dbuf_slice(display, slice) {
> -			if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
> -			    old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
> +			if (old_dbuf_bw->max_bw[slice] != new_dbuf_bw->max_bw[slice] ||
> +			    old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice])
>  				return true;
>  		}
>  
> @@ -1185,7 +1185,7 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
>  {
>  	struct intel_display *display = to_intel_display(crtc);
>  	struct drm_i915_private *i915 = to_i915(display->drm);
> -	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> +	struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[crtc->pipe];
>  	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
>  	enum dbuf_slice slice;
>  
> @@ -1194,8 +1194,8 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
>  	 * equal share of the total bw to each plane.
>  	 */
>  	for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {
> -		crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
> -		crtc_bw->active_planes[slice] |= BIT(plane_id);
> +		dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate);
> +		dbuf_bw->active_planes[slice] |= BIT(plane_id);
>  	}
>  }
>  
> @@ -1204,10 +1204,10 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> +	struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[crtc->pipe];
>  	enum plane_id plane_id;
>  
> -	memset(crtc_bw, 0, sizeof(*crtc_bw));
> +	memset(dbuf_bw, 0, sizeof(*dbuf_bw));
>  
>  	if (!crtc_state->hw.active)
>  		return;
> @@ -1249,10 +1249,10 @@ intel_bw_dbuf_min_cdclk(struct intel_display *display,
>  		 * equal share of the total bw to each plane.
>  		 */
>  		for_each_pipe(display, pipe) {
> -			const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
> +			const struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[pipe];
>  
> -			max_bw = max(crtc_bw->max_bw[slice], max_bw);
> -			num_active_planes += hweight8(crtc_bw->active_planes[slice]);
> +			max_bw = max(dbuf_bw->max_bw[slice], max_bw);
> +			num_active_planes += hweight8(dbuf_bw->active_planes[slice]);
>  		}
>  		max_bw *= num_active_planes;

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 15c2377193f7..b34db55f5a7e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1157,15 +1157,15 @@  static bool intel_bw_state_changed(struct intel_display *display,
 	enum pipe pipe;
 
 	for_each_pipe(display, pipe) {
-		const struct intel_dbuf_bw *old_crtc_bw =
+		const struct intel_dbuf_bw *old_dbuf_bw =
 			&old_bw_state->dbuf_bw[pipe];
-		const struct intel_dbuf_bw *new_crtc_bw =
+		const struct intel_dbuf_bw *new_dbuf_bw =
 			&new_bw_state->dbuf_bw[pipe];
 		enum dbuf_slice slice;
 
 		for_each_dbuf_slice(display, slice) {
-			if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
-			    old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
+			if (old_dbuf_bw->max_bw[slice] != new_dbuf_bw->max_bw[slice] ||
+			    old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice])
 				return true;
 		}
 
@@ -1185,7 +1185,7 @@  static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
 {
 	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *i915 = to_i915(display->drm);
-	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+	struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[crtc->pipe];
 	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
 	enum dbuf_slice slice;
 
@@ -1194,8 +1194,8 @@  static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
 	 * equal share of the total bw to each plane.
 	 */
 	for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {
-		crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
-		crtc_bw->active_planes[slice] |= BIT(plane_id);
+		dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate);
+		dbuf_bw->active_planes[slice] |= BIT(plane_id);
 	}
 }
 
@@ -1204,10 +1204,10 @@  static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+	struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[crtc->pipe];
 	enum plane_id plane_id;
 
-	memset(crtc_bw, 0, sizeof(*crtc_bw));
+	memset(dbuf_bw, 0, sizeof(*dbuf_bw));
 
 	if (!crtc_state->hw.active)
 		return;
@@ -1249,10 +1249,10 @@  intel_bw_dbuf_min_cdclk(struct intel_display *display,
 		 * equal share of the total bw to each plane.
 		 */
 		for_each_pipe(display, pipe) {
-			const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
+			const struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[pipe];
 
-			max_bw = max(crtc_bw->max_bw[slice], max_bw);
-			num_active_planes += hweight8(crtc_bw->active_planes[slice]);
+			max_bw = max(dbuf_bw->max_bw[slice], max_bw);
+			num_active_planes += hweight8(dbuf_bw->active_planes[slice]);
 		}
 		max_bw *= num_active_planes;

[v2,02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/

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