From patchwork Mon Apr 7 14:23:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19743C369A2 for ; Mon, 7 Apr 2025 14:39:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A839010E4B6; Mon, 7 Apr 2025 14:39:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nqhJT4Ld"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 52D0A10E4AE; Mon, 7 Apr 2025 14:39:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744036755; x=1775572755; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+f2VD6I1HJb49xVuDR0quwpQ60KE9eLOLMy6x8GhTRE=; b=nqhJT4LdMjFgC32UeDUjCmNVoUwmdvzRer9wPgefVKcluMFsulmCNoD7 xkENJenu/9pSLgmOMa3HqNhdFcMkSdaIiW7wSKFm+dQsWP7OoiSmWCdoF wp05hY7wGd+9D6zrOWCvpgokgMdFVA0r42def4PN95zdP7OsMg3fpx5SA uhRRRq8sdKOVNPVzOwsdMn5jjKvEqYSLrU39AxkNY0gMycZMoF8KcjVxN q12sZDnKDb8lKeRpy/8IW7rR1HVzkgIA1V+mLmu5zM4TiIS0Qm3NVjC1d rx4f+rM84XP8Ty6Xa8VSdw9cDeImAkyn2CsiitOSt42jHhgOMDnVWXzuP Q==; X-CSE-ConnectionGUID: jeXX42gXQ5S02cykSGQp2A== X-CSE-MsgGUID: Rwh/fWHKRo2bHhpvH3uQ1w== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572409" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572409" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:15 -0700 X-CSE-ConnectionGUID: /N11PhcZSVOPNF2N3BBngQ== X-CSE-MsgGUID: YuE8JhwsRwC4jKdndCAbyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963646" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:13 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 02/11] drm/i915/dsb: Extract assert_dsb_tail_is_aligned() Date: Mon, 7 Apr 2025 19:53:50 +0530 Message-Id: <20250407142359.1398410-3-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the DSB tail alignment checks into helper. We already have two uses of this, and soo we'll get a third. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index c166e02b8af0..08e3bbea1a67 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -204,6 +204,15 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb) crtc->base.base.id, crtc->base.name, dsb->id); } +static bool assert_dsb_tail_is_aligned(struct intel_dsb *dsb) +{ + struct intel_crtc *crtc = dsb->crtc; + struct intel_display *display = to_intel_display(crtc->base.dev); + + return !drm_WARN_ON(display->drm, + !IS_ALIGNED(dsb->free_pos * 4, CACHELINE_BYTES)); +} + static void intel_dsb_dump(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; @@ -621,10 +630,11 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) return; - tail = chained_dsb->free_pos * 4; - if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + if (!assert_dsb_tail_is_aligned(chained_dsb)) return; + tail = chained_dsb->free_pos * 4; + intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), ctrl | DSB_ENABLE); @@ -695,10 +705,11 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, enum pipe pipe = crtc->pipe; u32 tail; - tail = dsb->free_pos * 4; - if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + if (!assert_dsb_tail_is_aligned(dsb)) return; + tail = dsb->free_pos * 4; + if (is_dsb_busy(display, pipe, dsb->id)) { drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", crtc->base.base.id, crtc->base.name, dsb->id);