From patchwork Mon Apr 7 14:23:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14040890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A63FC36010 for ; Mon, 7 Apr 2025 14:39:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 99F9910E4B8; Mon, 7 Apr 2025 14:39:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nTbjKn44"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC8B710E4B9; Mon, 7 Apr 2025 14:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744036760; x=1775572760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hr8e+gyrDYvVWnYtttP1dVh+Rj6nKMUGG6hx8TlljY0=; b=nTbjKn44i0m1z1jIzPWq2ML7WlsI61JkXxxT5P/KtfwCsnHKOMeCkVn+ ieVDls+5+JMHgOEDadZpZiE1ignte32/En6UBhhl46lNpXueC188V0PDs 2EJyFFU7owgI7T7Kc+fQNYcaSRm/z1gJPulzSfqkYko4ZRQe8VC5rliE3 8cdtuhBr9n8VOdSqCFcVC4HR09ita6L/fNsmVmqHQX72Smt4OHvQqLklj qNgiqUGdNBtj2ukxQ59fWTfaODSLb8sqCD2Z3aXc0deHKIsY6j6AF7lfv 6vbq4RmUynrgPlkMpiXxPXgPdZo+5yCp0/n12AoBLuIIwnNqQPibJel2a Q==; X-CSE-ConnectionGUID: nvIHeEtFQE+UBEC5bG5TBA== X-CSE-MsgGUID: fa9IQPFLQgW25OeTH1zDPQ== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44572417" X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="44572417" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 07:39:20 -0700 X-CSE-ConnectionGUID: vd4Bc4QbRqOUJ4g/DK6Low== X-CSE-MsgGUID: 2/AL+MakR9OZYkFPPd8+Mg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,194,1739865600"; d="scan'208";a="158963673" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by fmviesa001.fm.intel.com with ESMTP; 07 Apr 2025 07:39:17 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 04/11] drm/i915/dsb: Implement intel_dsb_gosub() Date: Mon, 7 Apr 2025 19:53:52 +0530 Message-Id: <20250407142359.1398410-5-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> References: <20250407142359.1398410-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add support for the new GOSUB DSB instruction (available on ptl+), which instructs the DSB to jump to a different buffer, executie the commands there, and then return execution to the next instruction in the original buffer. There are a few alignment related workarounds that need to be dealt with when emitting GOSUB instruction. v2: Right shift head and tail pointer passed to gosub command (chaitanya) Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 52 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 2 + 2 files changed, 54 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 0de15e3a9a56..2cda6fc7857b 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -93,6 +93,9 @@ struct intel_dsb { /* see DSB_REG_VALUE_MASK */ #define DSB_OPCODE_POLL 0xA /* see DSB_REG_VALUE_MASK */ +#define DSB_OPCODE_GOSUB 0xC /* ptl+ */ +#define DSB_GOSUB_HEAD_SHIFT 26 +#define DSB_GOSUB_TAIL_SHIFT 0 static bool pre_commit_is_vrr_active(struct intel_atomic_state *state, struct intel_crtc *crtc) @@ -533,6 +536,55 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb) dsb->free_pos = aligned_tail / 4; } +static void intel_dsb_gosub_align(struct intel_dsb *dsb) +{ + u32 aligned_tail, tail; + + intel_dsb_ins_align(dsb); + + tail = dsb->free_pos * 4; + aligned_tail = ALIGN(tail, CACHELINE_BYTES); + + /* + * "The GOSUB instruction cannot be placed in + * cacheline QW slot 6 or 7 (numbered 0-7)" + */ + if (aligned_tail - tail <= 2 * 8) + intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, + aligned_tail - tail); + + dsb->free_pos = aligned_tail / 4; +} + +void intel_dsb_gosub(struct intel_dsb *dsb, + struct intel_dsb *sub_dsb) +{ + struct intel_crtc *crtc = dsb->crtc; + struct intel_display *display = to_intel_display(crtc->base.dev); + u64 head_tail; + + if (drm_WARN_ON(display->drm, dsb->id != sub_dsb->id)) + return; + + if (!assert_dsb_tail_is_aligned(sub_dsb)) + return; + + intel_dsb_gosub_align(dsb); + + head_tail = ((u64)(intel_dsb_head(sub_dsb) >> 6) << DSB_GOSUB_HEAD_SHIFT) | + ((u64)(intel_dsb_tail(sub_dsb) >> 6) << DSB_GOSUB_TAIL_SHIFT); + + intel_dsb_emit(dsb, lower_32_bits(head_tail), + (DSB_OPCODE_GOSUB << DSB_OPCODE_SHIFT) | + upper_32_bits(head_tail)); + + /* + * "NOTE: the instructions within the cacheline + * FOLLOWING the GOSUB instruction must be NOPs." + */ + intel_dsb_align_tail(dsb); +} + void intel_dsb_finish(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index e843c52bf97c..8b2cf0a7b7e6 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -57,6 +57,8 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, void intel_dsb_poll(struct intel_dsb *dsb, i915_reg_t reg, u32 mask, u32 val, int wait_us, int count); +void intel_dsb_gosub(struct intel_dsb *dsb, + struct intel_dsb *sub_dsb); void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb,