From patchwork Tue Apr 8 11:00:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 14042825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FBF7C369A4 for ; Tue, 8 Apr 2025 11:15:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 027AE10E662; Tue, 8 Apr 2025 11:15:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ClAEn504"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id A5D5610E660; Tue, 8 Apr 2025 11:15:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744110941; x=1775646941; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=314mqfDtjNu5mtNipiXbkfIWSGIVATmO2SWZYbJ+pPA=; b=ClAEn504MhiVQOzmBvwUm5Ud0J+PZfmJ7QFVEQoLRQdpPsfmGeNQB1PG AOxtcWYgFZd3o5qAoewcFwtFYd7N1Bgmq81cmOVqfioB333fiSuSMUUxr mcJa+DG84PTiBGbpaLgK9oUgREtbXzDJrmPYUN3hnRkBfU+2LKIWCNiPF 3RvGO7ygxIS4jUhJDXWgvsa+UqZkAEqMsP2Gt6gJf70pQWmzkh8rWAQhT 7pOXjKrV5LCzFHZdtU8xIk6kYOjSXhK9lCQmqSe2XXqty9/67nKh5Lk2h Z9yRjJ3Hog2f8Syd4FDe9QWyIIrLR8d6kORvhJy4cv0Sbf/3N+Lx28qiZ Q==; X-CSE-ConnectionGUID: ABoWMecAQnSTJThoGaCBCQ== X-CSE-MsgGUID: 8N2IoNSpTRaAB0BODQX6tg== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="45655918" X-IronPort-AV: E=Sophos;i="6.15,197,1739865600"; d="scan'208";a="45655918" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2025 04:15:41 -0700 X-CSE-ConnectionGUID: xHRrEsK0QPmc7ipc8H8omw== X-CSE-MsgGUID: H/zS+wRGTnGzdTbF8yg1pQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,197,1739865600"; d="scan'208";a="133209975" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by orviesa004.jf.intel.com with ESMTP; 08 Apr 2025 04:15:38 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, animesh.manna@intel.com Subject: [PATCH 03/11] drm/i915/dsb: Extract intel_dsb_{head,tail}() Date: Tue, 8 Apr 2025 16:30:14 +0530 Message-Id: <20250408110022.1907802-4-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250408110022.1907802-1-chaitanya.kumar.borah@intel.com> References: <20250408110022.1907802-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the code that calculates the DSB_HEAD/TAIL register values into small helpers. We already have two copies of this, and soon there will be a third. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 08e3bbea1a67..0de15e3a9a56 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -237,6 +237,16 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe, return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; } +static unsigned int intel_dsb_head(struct intel_dsb *dsb) +{ + return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); +} + +static unsigned int intel_dsb_tail(struct intel_dsb *dsb) +{ + return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + dsb->free_pos * 4; +} + static void intel_dsb_ins_align(struct intel_dsb *dsb) { /* @@ -625,7 +635,6 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state->base.dev); struct intel_crtc *crtc = dsb->crtc; enum pipe pipe = crtc->pipe; - u32 tail; if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) return; @@ -633,8 +642,6 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, if (!assert_dsb_tail_is_aligned(chained_dsb)) return; - tail = chained_dsb->free_pos * 4; - intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), ctrl | DSB_ENABLE); @@ -655,10 +662,10 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, } intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), - intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf)); + intel_dsb_head(chained_dsb)); intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), - intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail); + intel_dsb_tail(chained_dsb)); if (ctrl & DSB_WAIT_FOR_VBLANK) { /* @@ -703,13 +710,10 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, struct intel_crtc *crtc = dsb->crtc; struct intel_display *display = to_intel_display(crtc->base.dev); enum pipe pipe = crtc->pipe; - u32 tail; if (!assert_dsb_tail_is_aligned(dsb)) return; - tail = dsb->free_pos * 4; - if (is_dsb_busy(display, pipe, dsb->id)) { drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", crtc->base.base.id, crtc->base.name, dsb->id); @@ -727,7 +731,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, dsb_error_int_en(display) | DSB_PROG_INT_EN); intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), - intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); + intel_dsb_head(dsb)); if (hw_dewake_scanline >= 0) { int diff, position; @@ -749,7 +753,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, } intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id), - intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); + intel_dsb_tail(dsb)); } /**