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[1/6] drm/i915/vga: Clean up VGACNTRL bits

Message ID 20250417114454.12836-2-ville.syrjala@linux.intel.com (mailing list archive)
State New
Headers show
Series drm/i915/vga: Clean up VGA plane handling | expand

Commit Message

Ville Syrjala April 17, 2025, 11:44 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT() & co. for the VGACNTRL register bits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Jani Nikula April 17, 2025, 12:45 p.m. UTC | #1 
On Thu, 17 Apr 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. for the VGACNTRL register bits.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 49beab8e324d..81765f27b258 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1814,9 +1814,10 @@
>  
>  /* VBIOS regs */
>  #define VGACNTRL		_MMIO(0x71400)
> -# define VGA_DISP_DISABLE			(1 << 31)
> -# define VGA_2X_MODE				(1 << 30)
> -# define VGA_PIPE_B_SELECT			(1 << 29)
> +#define   VGA_DISP_DISABLE			REG_BIT(31)
> +#define   VGA_2X_MODE				REG_BIT(30)
> +#define   VGA_PIPE_SEL_MASK			REG_BIT(29)
> +#define   VGA_PIPE_SEL(pipe)			REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe))
>  
>  #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 49beab8e324d..81765f27b258 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1814,9 +1814,10 @@ 
 
 /* VBIOS regs */
 #define VGACNTRL		_MMIO(0x71400)
-# define VGA_DISP_DISABLE			(1 << 31)
-# define VGA_2X_MODE				(1 << 30)
-# define VGA_PIPE_B_SELECT			(1 << 29)
+#define   VGA_DISP_DISABLE			REG_BIT(31)
+#define   VGA_2X_MODE				REG_BIT(30)
+#define   VGA_PIPE_SEL_MASK			REG_BIT(29)
+#define   VGA_PIPE_SEL(pipe)			REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe))
 
 #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)