| Message ID | 24ef61574e5af12cd86d5b85afbfbd4ac2f9de25.1613054234.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/edp: enable eDP Multi-SST Operation (MSO) | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula > Sent: Thursday, February 11, 2021 8:22 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani <jani.nikula@intel.com>; Varide, Nischal <nischal.varide@intel.com> > Subject: [Intel-gfx] [PATCH v3 4/9] drm/i915/edp: read sink MSO configuration for > eDP 1.4+ > > Read and debug log the eDP sink MSO configuration. Do not actually do anything > with the information yet besides logging. > > FIXME: The pixel overlap is present in DisplayID 2.0, but we don't have parsing for > that. Assume zero for now. We could also add quirks for non-zero pixel overlap > before DisplayID 2.0 parsing. > > v3: Add placeholder for pixel overlap. > > v2: Rename intel_dp_mso_init -> intel_edp_mso_init Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Cc: Nischal Varide <nischal.varide@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 2 ++ > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++ > 2 files changed, 35 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index ebaa9d0ed376..71611b596c88 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1487,6 +1487,8 @@ struct intel_dp { > int max_link_lane_count; > /* Max rate for the current link */ > int max_link_rate; > + int mso_link_count; > + int mso_pixel_overlap; > /* sink or branch descriptor */ > struct drm_dp_desc desc; > struct drm_dp_aux aux; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 8d7ca03453e5..48e65b9a967a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -3516,6 +3516,37 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp > *intel_dp) > } > } > > +static void intel_edp_mso_init(struct intel_dp *intel_dp) { > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + u8 mso; > + > + if (intel_dp->edp_dpcd[0] < DP_EDP_14) > + return; > + > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, > &mso) != 1) { > + drm_err(&i915->drm, "Failed to read MSO cap\n"); > + return; > + } > + > + /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ > + mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; > + if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { > + drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso); > + mso = 0; > + } > + > + if (mso) { > + drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n", > + mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso); > + drm_err(&i915->drm, "No source MSO support, disabling\n"); > + mso = 0; > + } > + > + intel_dp->mso_link_count = mso; > + intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */ > +} > + > static bool > intel_edp_init_dpcd(struct intel_dp *intel_dp) { @@ -3599,6 +3630,8 @@ > intel_edp_init_dpcd(struct intel_dp *intel_dp) > */ > intel_edp_init_source_oui(intel_dp, true); > > + intel_edp_mso_init(intel_dp); > + > return true; > } > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ebaa9d0ed376..71611b596c88 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1487,6 +1487,8 @@ struct intel_dp { int max_link_lane_count; /* Max rate for the current link */ int max_link_rate; + int mso_link_count; + int mso_pixel_overlap; /* sink or branch descriptor */ struct drm_dp_desc desc; struct drm_dp_aux aux; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8d7ca03453e5..48e65b9a967a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3516,6 +3516,37 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) } } +static void intel_edp_mso_init(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u8 mso; + + if (intel_dp->edp_dpcd[0] < DP_EDP_14) + return; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { + drm_err(&i915->drm, "Failed to read MSO cap\n"); + return; + } + + /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ + mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; + if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { + drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso); + mso = 0; + } + + if (mso) { + drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n", + mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso); + drm_err(&i915->drm, "No source MSO support, disabling\n"); + mso = 0; + } + + intel_dp->mso_link_count = mso; + intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */ +} + static bool intel_edp_init_dpcd(struct intel_dp *intel_dp) { @@ -3599,6 +3630,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) */ intel_edp_init_source_oui(intel_dp, true); + intel_edp_mso_init(intel_dp); + return true; }
Read and debug log the eDP sink MSO configuration. Do not actually do anything with the information yet besides logging. FIXME: The pixel overlap is present in DisplayID 2.0, but we don't have parsing for that. Assume zero for now. We could also add quirks for non-zero pixel overlap before DisplayID 2.0 parsing. v3: Add placeholder for pixel overlap. v2: Rename intel_dp_mso_init -> intel_edp_mso_init Cc: Nischal Varide <nischal.varide@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- .../drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++ 2 files changed, 35 insertions(+)