From patchwork Mon May 25 15:57:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "G, Pallavi" X-Patchwork-Id: 6475991 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5319CC0020 for ; Mon, 25 May 2015 15:57:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6E09C2039C for ; Mon, 25 May 2015 15:57:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 81B382038F for ; Mon, 25 May 2015 15:57:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECA976E1D6; Mon, 25 May 2015 08:57:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 1FB566E1D6 for ; Mon, 25 May 2015 08:57:24 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 25 May 2015 08:57:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,492,1427785200"; d="scan'208";a="734975081" Received: from pgsmsx107.gar.corp.intel.com ([10.221.44.105]) by orsmga002.jf.intel.com with ESMTP; 25 May 2015 08:57:03 -0700 Received: from bgsmsx101.gar.corp.intel.com (10.223.4.170) by PGSMSX107.gar.corp.intel.com (10.221.44.105) with Microsoft SMTP Server (TLS) id 14.3.224.2; Mon, 25 May 2015 23:57:02 +0800 Received: from bgsmsx103.gar.corp.intel.com ([169.254.4.3]) by BGSMSX101.gar.corp.intel.com ([169.254.1.34]) with mapi id 14.03.0224.002; Mon, 25 May 2015 21:27:01 +0530 From: "G, Pallavi" To: "Roper, Matthew D" , "intel-gfx@lists.freedesktop.org" Thread-Topic: [Intel-gfx] [RFC 14/15] drm/i915: Program atomic watermarks via vblank job Thread-Index: AQHQk2umVvbFq+FWwEuDZHiiT5P/dJ2M3wvw Date: Mon, 25 May 2015 15:57:01 +0000 Message-ID: <288F2AD7A5BB644A8E17E7267429B13C10DC2EA7@BGSMSX103.gar.corp.intel.com> References: <1432174347-19138-1-git-send-email-matthew.d.roper@intel.com> <1432174347-19138-15-git-send-email-matthew.d.roper@intel.com> In-Reply-To: <1432174347-19138-15-git-send-email-matthew.d.roper@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Subject: Re: [Intel-gfx] [RFC 14/15] drm/i915: Program atomic watermarks via vblank job X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Why don’t we do this wm update as part of the fb unpin what is the need for wq here. May add some latency Please clarify Thanks, Pallavi -----Original Message----- From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Matt Roper Sent: Thursday, May 21, 2015 7:42 AM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [RFC 14/15] drm/i915: Program atomic watermarks via vblank job Use the new vblank job infrastructure to schedule watermark programming to happen when the next vblank occurs. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 7 +++++++ drivers/gpu/drm/i915/intel_display.c | 38 +++++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_pm.c | 1 + 3 files changed, 41 insertions(+), 5 deletions(-) -- 1.8.5.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d577eba..5134101 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -569,6 +569,7 @@ struct drm_i915_display_funcs { struct drm_crtc *crtc, uint32_t sprite_width, uint32_t sprite_height, int pixel_size, bool enable, bool scaled); + void (*program_watermarks)(struct drm_i915_private *dev_priv); void (*modeset_global_resources)(struct drm_atomic_state *state); /* Returns the active state of the crtc, and if the crtc is active, * fills out the pipe-config with the hw state. */ @@ -2494,6 +2495,12 @@ struct drm_i915_cmd_table { #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) +/* + * FIXME: Only some platforms have been transitioned to atomic +watermark + * updates so far. + */ +#define HAS_ATOMIC_WM(dev_priv) (dev_priv->display.program_watermarks +!= NULL) + #define GT_FREQUENCY_MULTIPLIER 50 #define GEN9_FREQ_SCALER 3 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9b56d07..b2012c9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13209,6 +13209,24 @@ intel_disable_primary_plane(struct drm_plane *plane, dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); } +static void +do_update_watermarks(struct intel_crtc *intel_crtc, + void *data, + bool early, + u32 seq) +{ + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + + /* + * If we fired early because the CRTC is turning off, there's no + * need to actually program watermarks. + */ + if (early) + return; + + dev_priv->display.program_watermarks(dev_priv); +} + static void intel_begin_crtc_commit(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -13251,7 +13269,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc) if (intel_crtc->atomic.pre_disable_primary) intel_pre_disable_primary(crtc); - if (intel_crtc->atomic.update_wm) + if (!HAS_ATOMIC_WM(dev_priv) && intel_crtc->atomic.update_wm) intel_update_watermarks(crtc); intel_runtime_pm_get(dev_priv); @@ -13270,6 +13288,15 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_plane *p; + /* + * If this platform supports atomic watermarks, schedule a job to + * update watermarks when the next vblank occurs. Otherwise, just + * update watermarks the old-fashioned way. + */ + if (HAS_ATOMIC_WM(dev_priv)) + intel_schedule_vblank_job(intel_crtc, do_update_watermarks, + NULL, dev_priv->wq, 1); + if (intel_crtc->atomic.evade) intel_pipe_update_end(intel_crtc, intel_crtc->atomic.start_vbl_count); @@ -13290,10 +13317,11 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc) if (intel_crtc->atomic.post_enable_primary) intel_post_enable_primary(crtc); - drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) - if (intel_crtc->atomic.update_sprite_watermarks & - (1 << drm_plane_index(p))) - intel_update_sprite_watermarks(p, crtc); + if (!HAS_ATOMIC_WM(dev_priv)) + drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) + if (intel_crtc->atomic.update_sprite_watermarks & + (1 << drm_plane_index(p))) + intel_update_sprite_watermarks(p, crtc); memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); } diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 27337fe..7f0a0c1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6626,6 +6626,7 @@ void intel_init_pm(struct drm_device *dev) dev_priv->display.update_wm = ilk_update_wm; dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; + dev_priv->display.program_watermarks = ilk_program_watermarks; } else { DRM_DEBUG_KMS("Failed to read display plane latency. " "Disable CxSR\n");