Message ID | 2a11577139f82f50058a2167404b82fa7c80cb39.1649871650.git.ashutosh.dixit@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/i915: Media freq factor and per-gt enhancements/fixes | expand |
Hi Ashutosh, On 2022-04-13 at 11:11:06 -0700, Ashutosh Dixit wrote: > Retrieve RP0 and RPn freq for media IP from PCODE and display in per-gt > sysfs. This patch adds the following files to gt/gtN sysfs: > * media_RP0_freq_mhz > * media_RPn_freq_mhz --------- ^ Can we keep it in lowercase ? So it will be like: media_rp0_freq_mhz media_rpn_freq_mhz Or is it merged with capital letters at other sysfs path ? Regards, Kamil > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Original-author: Dale B Stimson <dale.b.stimson@intel.com> > Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 47 +++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 15 +++++++ > 2 files changed, 62 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > index 2b1cd6a01724..2a3398003933 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > @@ -12,6 +12,7 @@ > #include "i915_sysfs.h" > #include "intel_gt.h" > #include "intel_gt_regs.h" > +#include "intel_pcode.h" > #include "intel_gt_sysfs.h" > #include "intel_gt_sysfs_pm.h" > #include "intel_rc6.h" > @@ -669,13 +670,59 @@ static ssize_t media_freq_factor_store(struct device *dev, > return err ?: count; > } > > +static ssize_t media_RP0_freq_mhz_show(struct device *dev, > + struct device_attribute *attr, > + char *buff) > +{ > + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name); > + u32 val; > + int err; > + > + err = __intel_gt_pcode_read(gt, XEHPSDV_PCODE_FREQUENCY_CONFIG, > + PCODE_MBOX_FC_SC_READ_FUSED_P0, > + PCODE_MBOX_DOMAIN_MEDIAFF, &val); > + > + if (err) > + return err; > + > + /* data_out - Fused P0 for domain ID in units of 50 MHz */ > + val *= GT_FREQUENCY_MULTIPLIER; > + > + return sysfs_emit(buff, "%u\n", val); > +} > + > +static ssize_t media_RPn_freq_mhz_show(struct device *dev, > + struct device_attribute *attr, > + char *buff) > +{ > + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name); > + u32 val; > + int err; > + > + err = __intel_gt_pcode_read(gt, XEHPSDV_PCODE_FREQUENCY_CONFIG, > + PCODE_MBOX_FC_SC_READ_FUSED_PN, > + PCODE_MBOX_DOMAIN_MEDIAFF, &val); > + > + if (err) > + return err; > + > + /* data_out - Fused P0 for domain ID in units of 50 MHz */ > + val *= GT_FREQUENCY_MULTIPLIER; > + > + return sysfs_emit(buff, "%u\n", val); > +} > + > static DEVICE_ATTR_RW(media_freq_factor); > static struct device_attribute dev_attr_media_freq_factor_scale = > __ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL); > +static DEVICE_ATTR_RO(media_RP0_freq_mhz); > +static DEVICE_ATTR_RO(media_RPn_freq_mhz); > > static const struct attribute *media_perf_power_attrs[] = { > &dev_attr_media_freq_factor.attr, > &dev_attr_media_freq_factor_scale.attr, > + &dev_attr_media_RP0_freq_mhz.attr, > + &dev_attr_media_RPn_freq_mhz.attr, > NULL > }; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0d5a4ecd374a..a45a776b2dae 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6753,6 +6753,21 @@ > #define DG1_UNCORE_GET_INIT_STATUS 0x0 > #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 > #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 > +#define XEHPSDV_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ > +/* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ > +#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 > +#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 > +/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ > +/* XEHPSDV_PCODE_FREQUENCY_CONFIG param2 */ > +#define PCODE_MBOX_DOMAIN_NONE 0x0 > +#define PCODE_MBOX_DOMAIN_GT 0x1 > +#define PCODE_MBOX_DOMAIN_HBM 0x2 > +#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 > +#define PCODE_MBOX_DOMAIN_MEDIA_SAMPLER 0x4 > +#define PCODE_MBOX_DOMAIN_SYSTOLIC_ARRAY 0x5 > +#define PCODE_MBOX_DOMAIN_CHIPLET 0x6 > +#define PCODE_MBOX_DOMAIN_BASE_CHIPLET_LINK 0x7 > +#define PCODE_MBOX_DOMAIN_BASE 0x8 > #define GEN6_PCODE_DATA _MMIO(0x138128) > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 > -- > 2.34.1 >
On Mon, 25 Apr 2022 02:39:42 -0700, Kamil Konieczny wrote: > > Hi Ashutosh, Hi Kamil, > On 2022-04-13 at 11:11:06 -0700, Ashutosh Dixit wrote: > > Retrieve RP0 and RPn freq for media IP from PCODE and display in per-gt > > sysfs. This patch adds the following files to gt/gtN sysfs: > > * media_RP0_freq_mhz > > * media_RPn_freq_mhz > --------- ^ > Can we keep it in lowercase ? So it will be like: > media_rp0_freq_mhz > media_rpn_freq_mhz > > Or is it merged with capital letters at other sysfs path ? Unfortunately that is the case as we can see below: $ ls -l /sys/class/drm/card0/gt/gt0/rps* -r--r--r-- 1 root root 4096 Jan 20 19:55 rps_RP0_freq_mhz -r--r--r-- 1 root root 4096 Jan 20 19:55 rps_RP1_freq_mhz -r--r--r-- 1 root root 4096 Jan 20 19:55 rps_RPn_freq_mhz We could have have discussed it before the other RPS patches were merged but I think at this point we'd need to maintain consistency with the previous naming scheme (the frequencies are actually known as RP0/RPn). Thanks. -- Ashutosh
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c index 2b1cd6a01724..2a3398003933 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c @@ -12,6 +12,7 @@ #include "i915_sysfs.h" #include "intel_gt.h" #include "intel_gt_regs.h" +#include "intel_pcode.h" #include "intel_gt_sysfs.h" #include "intel_gt_sysfs_pm.h" #include "intel_rc6.h" @@ -669,13 +670,59 @@ static ssize_t media_freq_factor_store(struct device *dev, return err ?: count; } +static ssize_t media_RP0_freq_mhz_show(struct device *dev, + struct device_attribute *attr, + char *buff) +{ + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name); + u32 val; + int err; + + err = __intel_gt_pcode_read(gt, XEHPSDV_PCODE_FREQUENCY_CONFIG, + PCODE_MBOX_FC_SC_READ_FUSED_P0, + PCODE_MBOX_DOMAIN_MEDIAFF, &val); + + if (err) + return err; + + /* data_out - Fused P0 for domain ID in units of 50 MHz */ + val *= GT_FREQUENCY_MULTIPLIER; + + return sysfs_emit(buff, "%u\n", val); +} + +static ssize_t media_RPn_freq_mhz_show(struct device *dev, + struct device_attribute *attr, + char *buff) +{ + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name); + u32 val; + int err; + + err = __intel_gt_pcode_read(gt, XEHPSDV_PCODE_FREQUENCY_CONFIG, + PCODE_MBOX_FC_SC_READ_FUSED_PN, + PCODE_MBOX_DOMAIN_MEDIAFF, &val); + + if (err) + return err; + + /* data_out - Fused P0 for domain ID in units of 50 MHz */ + val *= GT_FREQUENCY_MULTIPLIER; + + return sysfs_emit(buff, "%u\n", val); +} + static DEVICE_ATTR_RW(media_freq_factor); static struct device_attribute dev_attr_media_freq_factor_scale = __ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL); +static DEVICE_ATTR_RO(media_RP0_freq_mhz); +static DEVICE_ATTR_RO(media_RPn_freq_mhz); static const struct attribute *media_perf_power_attrs[] = { &dev_attr_media_freq_factor.attr, &dev_attr_media_freq_factor_scale.attr, + &dev_attr_media_RP0_freq_mhz.attr, + &dev_attr_media_RPn_freq_mhz.attr, NULL }; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0d5a4ecd374a..a45a776b2dae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6753,6 +6753,21 @@ #define DG1_UNCORE_GET_INIT_STATUS 0x0 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 +#define XEHPSDV_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ +/* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ +#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 +#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 +/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ +/* XEHPSDV_PCODE_FREQUENCY_CONFIG param2 */ +#define PCODE_MBOX_DOMAIN_NONE 0x0 +#define PCODE_MBOX_DOMAIN_GT 0x1 +#define PCODE_MBOX_DOMAIN_HBM 0x2 +#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 +#define PCODE_MBOX_DOMAIN_MEDIA_SAMPLER 0x4 +#define PCODE_MBOX_DOMAIN_SYSTOLIC_ARRAY 0x5 +#define PCODE_MBOX_DOMAIN_CHIPLET 0x6 +#define PCODE_MBOX_DOMAIN_BASE_CHIPLET_LINK 0x7 +#define PCODE_MBOX_DOMAIN_BASE 0x8 #define GEN6_PCODE_DATA _MMIO(0x138128) #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16