From patchwork Tue Oct 30 11:56:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 10660819 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ACC8714BD for ; Tue, 30 Oct 2018 11:57:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A1E812A24B for ; Tue, 30 Oct 2018 11:57:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9668A2A265; Tue, 30 Oct 2018 11:57:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4CCB42A24B for ; Tue, 30 Oct 2018 11:57:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6066E6E0A6; Tue, 30 Oct 2018 11:57:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 154A36E065 for ; Tue, 30 Oct 2018 11:57:42 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2018 04:57:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,444,1534834800"; d="scan'208";a="103754152" Received: from jnikula-mobl3.fi.intel.com (HELO localhost) ([10.237.72.61]) by fmsmga001.fm.intel.com with ESMTP; 30 Oct 2018 04:57:40 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 30 Oct 2018 13:56:43 +0200 Message-Id: <306b7ed2758a81833fb3e1ebde146dc1a2e7e93b.1540900289.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v8 37/38] drm/i915/icl: Consider DSI for getting transcoder state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Madhav Chauhan For Gen11 DSI, we use similar registers like for eDP to find if DSI encoder is connected or not to a pipe. This patch refactors existing hsw_get_transcoder_state() to handle this. Signed-off-by: Madhav Chauhan Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1d46f06ede37..1670646240ba 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9366,6 +9366,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(dev); enum intel_display_power_domain power_domain; u32 tmp; + bool is_dsi = false; + bool is_edp = false; /* * The pipe->transcoder mapping is fixed with the exception of the eDP @@ -9378,26 +9380,39 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, * consistency and less surprising code; it's in always on power). */ tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); - if (tmp & TRANS_DDI_FUNC_ENABLE) { - enum pipe trans_edp_pipe; + if (tmp & TRANS_DDI_FUNC_ENABLE) + is_edp = true; + + if (IS_ICELAKE(dev_priv)) { + tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_DSI_0)); + if (tmp & TRANS_DDI_FUNC_ENABLE) + is_dsi = true; + } + + if (is_edp || is_dsi) { + enum pipe trans_pipe; switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { default: WARN(1, "unknown pipe linked to edp transcoder\n"); /* fall through */ case TRANS_DDI_EDP_INPUT_A_ONOFF: case TRANS_DDI_EDP_INPUT_A_ON: - trans_edp_pipe = PIPE_A; + trans_pipe = PIPE_A; break; case TRANS_DDI_EDP_INPUT_B_ONOFF: - trans_edp_pipe = PIPE_B; + trans_pipe = PIPE_B; break; case TRANS_DDI_EDP_INPUT_C_ONOFF: - trans_edp_pipe = PIPE_C; + trans_pipe = PIPE_C; break; } - if (trans_edp_pipe == crtc->pipe) - pipe_config->cpu_transcoder = TRANSCODER_EDP; + if (trans_pipe == crtc->pipe) { + if (is_edp) + pipe_config->cpu_transcoder = TRANSCODER_EDP; + else if (is_dsi) + pipe_config->cpu_transcoder = TRANSCODER_DSI_0; + } } power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);