| Message ID | 323345ceb2f52a10b684be066393b4ff9753fbf5.1378208439.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Sep 03, 2013 at 02:43:38PM +0300, Jani Nikula wrote: > Remove dupes, add VLV port B. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 7 +------ > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > 2 files changed, 3 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c7f2da3..accbd1f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4449,6 +4449,7 @@ > #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) > #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) > #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) > +#define PANEL_PORT_SELECT_DPB_VLV (1 << 30) The DPC value is the same as on other platforms, but since the other values are not valid for VLV it might be a bit cleaner to define also DPC_VLV here. I'm won't insist though if you don't want it there. > #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) > #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) > > @@ -4480,7 +4481,6 @@ > #define PANEL_PORT_SELECT_MASK (3 << 30) > #define PANEL_PORT_SELECT_LVDS (0 << 30) > #define PANEL_PORT_SELECT_DPA (1 << 30) > -#define EDP_PANEL (1 << 30) Hmm. Yeah, the EDP bit is there only for CTG, and we don't do eDP on CTG. I must assume such hardware never existed. So w/ or w/o the DPC_VLV thing: Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > #define PANEL_PORT_SELECT_DPC (2 << 30) > #define PANEL_PORT_SELECT_DPD (3 << 30) > #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) > @@ -4489,11 +4489,6 @@ > #define PANEL_LIGHT_ON_DELAY_SHIFT 0 > > #define PCH_PP_OFF_DELAYS 0xc720c > -#define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30) > -#define PANEL_POWER_PORT_LVDS (0 << 30) > -#define PANEL_POWER_PORT_DP_A (1 << 30) > -#define PANEL_POWER_PORT_DP_C (2 << 30) > -#define PANEL_POWER_PORT_DP_D (3 << 30) > #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) > #define PANEL_POWER_DOWN_DELAY_SHIFT 16 > #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index adbe7bc..0ba72f1 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3281,9 +3281,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, > port_sel = I915_READ(pp_on_reg) & 0xc0000000; > } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { > if (dp_to_dig_port(intel_dp)->port == PORT_A) > - port_sel = PANEL_POWER_PORT_DP_A; > + port_sel = PANEL_PORT_SELECT_DPA; > else > - port_sel = PANEL_POWER_PORT_DP_D; > + port_sel = PANEL_PORT_SELECT_DPD; > } > > pp_on |= port_sel; > -- > 1.7.9.5
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c7f2da3..accbd1f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4449,6 +4449,7 @@ #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) +#define PANEL_PORT_SELECT_DPB_VLV (1 << 30) #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) @@ -4480,7 +4481,6 @@ #define PANEL_PORT_SELECT_MASK (3 << 30) #define PANEL_PORT_SELECT_LVDS (0 << 30) #define PANEL_PORT_SELECT_DPA (1 << 30) -#define EDP_PANEL (1 << 30) #define PANEL_PORT_SELECT_DPC (2 << 30) #define PANEL_PORT_SELECT_DPD (3 << 30) #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) @@ -4489,11 +4489,6 @@ #define PANEL_LIGHT_ON_DELAY_SHIFT 0 #define PCH_PP_OFF_DELAYS 0xc720c -#define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30) -#define PANEL_POWER_PORT_LVDS (0 << 30) -#define PANEL_POWER_PORT_DP_A (1 << 30) -#define PANEL_POWER_PORT_DP_C (2 << 30) -#define PANEL_POWER_PORT_DP_D (3 << 30) #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) #define PANEL_POWER_DOWN_DELAY_SHIFT 16 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index adbe7bc..0ba72f1 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3281,9 +3281,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, port_sel = I915_READ(pp_on_reg) & 0xc0000000; } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { if (dp_to_dig_port(intel_dp)->port == PORT_A) - port_sel = PANEL_POWER_PORT_DP_A; + port_sel = PANEL_PORT_SELECT_DPA; else - port_sel = PANEL_POWER_PORT_DP_D; + port_sel = PANEL_PORT_SELECT_DPD; } pp_on |= port_sel;
Remove dupes, add VLV port B. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 7 +------ drivers/gpu/drm/i915/intel_dp.c | 4 ++-- 2 files changed, 3 insertions(+), 8 deletions(-)