diff mbox series

[2/9] drm/i915/dp: fix style issues in intel_dp_test.c

Message ID 330f918a3b4fe6dd156dd89ee26c56cf8ae8ec31.1726833193.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/dp: clean up DP testing | expand

Commit Message

Jani Nikula Sept. 20, 2024, 11:56 a.m. UTC 
Apply some style fixes on top of the previous code movement.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_test.c | 26 ++++++++++----------
 1 file changed, 13 insertions(+), 13 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.c b/drivers/gpu/drm/i915/display/intel_dp_test.c
index 41cb05f44670..0a49b15f99e6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_test.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_test.c
@@ -29,7 +29,8 @@  intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 	if (intel_dp->compliance.test_data.bpc != 0) {
 		int bpp = 3 * intel_dp->compliance.test_data.bpc;
 
-		limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
+		limits->pipe.min_bpp = bpp;
+		limits->pipe.max_bpp = bpp;
 		pipe_config->dither_force_disable = bpp == 6 * 3;
 
 		drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
@@ -47,20 +48,20 @@  intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 			index = intel_dp_rate_index(intel_dp->common_rates,
 						    intel_dp->num_common_rates,
 						    intel_dp->compliance.test_link_rate);
-			if (index >= 0)
-				limits->min_rate = limits->max_rate =
-					intel_dp->compliance.test_link_rate;
-			limits->min_lane_count = limits->max_lane_count =
-				intel_dp->compliance.test_lane_count;
+			if (index >= 0) {
+				limits->min_rate = intel_dp->compliance.test_link_rate;
+				limits->max_rate = intel_dp->compliance.test_link_rate;
+			}
+			limits->min_lane_count = intel_dp->compliance.test_lane_count;
+			limits->max_lane_count = intel_dp->compliance.test_lane_count;
 		}
 	}
 }
 
 /* Compliance test status bits  */
-#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
-#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
-#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
-#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
+#define INTEL_DP_RESOLUTION_PREFERRED	1
+#define INTEL_DP_RESOLUTION_STANDARD	2
+#define INTEL_DP_RESOLUTION_FAILSAFE	3
 
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
@@ -169,8 +170,7 @@  static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	struct drm_connector *connector = &intel_connector->base;
 
-	if (intel_connector->detect_edid == NULL ||
-	    connector->edid_corrupt ||
+	if (!intel_connector->detect_edid || connector->edid_corrupt ||
 	    intel_dp->aux.i2c_defer_count > 6) {
 		/* Check EDID read for NACKs, DEFERs and corruption
 		 * (DP CTS 1.2 Core r1.1)
@@ -180,7 +180,7 @@  static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 		 * Use failsafe mode for all cases
 		 */
 		if (intel_dp->aux.i2c_nack_count > 0 ||
-			intel_dp->aux.i2c_defer_count > 0)
+		    intel_dp->aux.i2c_defer_count > 0)
 			drm_dbg_kms(&i915->drm,
 				    "EDID read had %d NACKs, %d DEFERs\n",
 				    intel_dp->aux.i2c_nack_count,