| Message ID | 46401f9df30907ba851b68d7772740d64fc6ee83.1643130139.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/dp, drm/i915: 128b/132b updates | expand |
On Tue, Jan 25, 2022 at 07:03:39PM +0200, Jani Nikula wrote: > The DP 2.0 errata changes DP_128B132B_TRAINING_AUX_RD_INTERVAL (DPCD > 0x2216) completely. Add a new function to read that. Follow-up will need > to clean up existing functions. > > v2: fix reversed interpretation of bit 7 meaning (Uma) > > Cc: Uma Shankar <uma.shankar@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/dp/drm_dp.c | 20 ++++++++++++++++++++ > include/drm/dp/drm_dp_helper.h | 3 +++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c > index 6d43325acca5..52c6da510142 100644 > --- a/drivers/gpu/drm/dp/drm_dp.c > +++ b/drivers/gpu/drm/dp/drm_dp.c > @@ -281,6 +281,26 @@ int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIV > } > EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); > > +/* Per DP 2.0 Errata */ > +int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) > +{ > + int unit; > + u8 val; > + > + if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { > + drm_err(aux->drm_dev, "%s: failed rd interval read\n", > + aux->name); > + /* default to max */ > + val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; > + } > + > + unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2; > + val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; > + > + return (val + 1) * unit * 1000; > +} > +EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval); > + > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h > index 98d020835b49..aa73dfc817ff 100644 > --- a/include/drm/dp/drm_dp_helper.h > +++ b/include/drm/dp/drm_dp_helper.h > @@ -1112,6 +1112,7 @@ struct drm_panel; > # define DP_UHBR13_5 (1 << 2) > > #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ > +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7) > # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f > # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00 > # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01 > @@ -1549,6 +1550,8 @@ void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > > +int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); > + > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); > > -- > 2.30.2
diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index 6d43325acca5..52c6da510142 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -281,6 +281,26 @@ int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIV } EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); +/* Per DP 2.0 Errata */ +int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) +{ + int unit; + u8 val; + + if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { + drm_err(aux->drm_dev, "%s: failed rd interval read\n", + aux->name); + /* default to max */ + val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; + } + + unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2; + val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; + + return (val + 1) * unit * 1000; +} +EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval); + void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 98d020835b49..aa73dfc817ff 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -1112,6 +1112,7 @@ struct drm_panel; # define DP_UHBR13_5 (1 << 2) #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7) # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01 @@ -1549,6 +1550,8 @@ void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); +int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); + u8 drm_dp_link_rate_to_bw_code(int link_rate); int drm_dp_bw_code_to_link_rate(u8 link_bw);
The DP 2.0 errata changes DP_128B132B_TRAINING_AUX_RD_INTERVAL (DPCD 0x2216) completely. Add a new function to read that. Follow-up will need to clean up existing functions. v2: fix reversed interpretation of bit 7 meaning (Uma) Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/dp/drm_dp.c | 20 ++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 3 +++ 2 files changed, 23 insertions(+)