From patchwork Sat Jul 28 00:19:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10547845 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D393C174A for ; Sat, 28 Jul 2018 00:20:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C19F72C4C7 for ; Sat, 28 Jul 2018 00:20:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B36CA2C547; Sat, 28 Jul 2018 00:20:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3108F2C4C7 for ; Sat, 28 Jul 2018 00:20:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5FB26E09F; Sat, 28 Jul 2018 00:20:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5E7DB6E09F for ; Sat, 28 Jul 2018 00:20:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jul 2018 17:20:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,411,1526367600"; d="scan'208";a="76623442" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga001.jf.intel.com with ESMTP; 27 Jul 2018 17:20:01 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 27 Jul 2018 17:20:01 -0700 Received: from fmsmsx108.amr.corp.intel.com ([169.254.9.10]) by FMSMSX110.amr.corp.intel.com ([169.254.14.196]) with mapi id 14.03.0319.002; Fri, 27 Jul 2018 17:20:00 -0700 From: "Souza, Jose" To: "intel-gfx@lists.freedesktop.org" Thread-Topic: [PATCH v2 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states Thread-Index: AQHUJgi4xaylIbJTVEK0/xsF5ha9yg== Date: Sat, 28 Jul 2018 00:19:59 +0000 Message-ID: <48b2e64b64f4fade1eabb56bbc724635f0a88ad7.camel@intel.com> References: <20180727233626.9216-1-jose.souza@intel.com> In-Reply-To: <20180727233626.9216-1-jose.souza@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.24.11.40] Content-ID: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Zanoni, Paulo R" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When returning from low power states the CSR firmware was not being loaded again in CNL and ICL. Also taking the opportunity to share the load call for gen >= 9, instead of calling it from each display_core_init() function. Changes from v1: Calling intel_csr_load_program() right after display_core_init(). Cc: Paulo Zanoni Cc: Anusha Srivatsa Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 9 ++++++--- drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +++--------- 2 files changed, 9 insertions(+), 12 deletions(-) static void skl_display_core_uninit(struct drm_i915_private *dev_priv) @@ -3140,9 +3137,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bxt_init_cdclk(dev_priv); gen9_dbuf_enable(dev_priv); - - if (resume && dev_priv->csr.dmc_payload) - intel_csr_load_program(dev_priv); } void bxt_display_core_uninit(struct drm_i915_private *dev_priv) @@ -3283,9 +3277,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 6. Enable DBUF */ gen9_dbuf_enable(dev_priv); - - if (resume && dev_priv->csr.dmc_payload) - intel_csr_load_program(dev_priv); } static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) @@ -3559,6 +3550,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) mutex_unlock(&power_domains->lock); } + if (INTEL_GEN(dev_priv) >= 9 && resume && dev_priv- >csr.dmc_payload) + intel_csr_load_program(dev_priv); + /* For now, we need the power well to be always enabled. */ intel_display_set_init_power(dev_priv, true); /* Disable power support if the user asked so. */ diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 18a45e7a3d7c..a42f0dfe19da 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2699,9 +2699,12 @@ static int intel_runtime_resume(struct device *kdev) if (IS_GEN9_LP(dev_priv)) { bxt_disable_dc9(dev_priv); bxt_display_core_init(dev_priv, true); - if (dev_priv->csr.dmc_payload && - (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) - gen9_enable_dc5(dev_priv); + if (dev_priv->csr.dmc_payload) { + intel_csr_load_program(dev_priv); + if (dev_priv->csr.allowed_dc_mask & + DC_STATE_EN_UPTO_DC5) + gen9_enable_dc5(dev_priv); + } } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { hsw_disable_pc8(dev_priv); } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index cf89141b2281..ebc084d90136 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3075,9 +3075,6 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, skl_init_cdclk(dev_priv); gen9_dbuf_enable(dev_priv); - - if (resume && dev_priv->csr.dmc_payload) - intel_csr_load_program(dev_priv); }