@@ -3369,6 +3374,7 @@ enum skl_disp_power_wells {
#define _GEN3_SDVOC 0x61160
#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
+#define HDMIB (dev_priv->info.display_mmio_offset + 0x61140)
#define GEN4_HDMIB GEN3_SDVOB
#define GEN4_HDMIC GEN3_SDVOC
#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
@@ -3378,6 +3384,7 @@ enum skl_disp_power_wells {
#define PCH_HDMIB PCH_SDVOB
#define PCH_HDMIC _MMIO(0xe1150)
#define PCH_HDMID _MMIO(0xe1160)
+#define PORT_ENABLE (1 << 31)
#define PORT_DFT_I9XX _MMIO(0x61150)
#define DC_BALANCE_RESET (1 << 25)