diff mbox series

[05/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS

Message ID 57285c891b10d4827423c20563f2b4a2632e65c1.1715183162.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/display: remove implicit dev_priv from VRR | expand

Commit Message

Jani Nikula May 8, 2024, 3:47 p.m. UTC
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VRR_STATUS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h          | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

Comments

Vivi, Rodrigo May 10, 2024, 1:50 a.m. UTC | #1
On Wed, May 08, 2024 at 06:47:51PM +0300, Jani Nikula wrote:
61;7600;1c> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VRR_STATUS register macro.
> 

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h          | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index fd0f0794f6dc..05cbd6e4fc60 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -282,7 +282,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>  
>  	intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
>  		       trans_vrr_ctl(old_crtc_state));
> -	intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
> +	intel_de_wait_for_clear(dev_priv,
> +				TRANS_VRR_STATUS(dev_priv, cpu_transcoder),
>  				VRR_STATUS_VRR_EN_LIVE, 1000);
>  	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9739ef525e13..df43b9eb5374 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1271,7 +1271,7 @@
>  #define _TRANS_VRR_STATUS_B		0x6142C
>  #define _TRANS_VRR_STATUS_C		0x6242C
>  #define _TRANS_VRR_STATUS_D		0x6342C
> -#define TRANS_VRR_STATUS(trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
> +#define TRANS_VRR_STATUS(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
>  #define   VRR_STATUS_VMAX_REACHED	REG_BIT(31)
>  #define   VRR_STATUS_NOFLIP_TILL_BNDR	REG_BIT(30)
>  #define   VRR_STATUS_FLIP_BEF_BNDR	REG_BIT(29)
> -- 
> 2.39.2
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index fd0f0794f6dc..05cbd6e4fc60 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -282,7 +282,8 @@  void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 
 	intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
 		       trans_vrr_ctl(old_crtc_state));
-	intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
+	intel_de_wait_for_clear(dev_priv,
+				TRANS_VRR_STATUS(dev_priv, cpu_transcoder),
 				VRR_STATUS_VRR_EN_LIVE, 1000);
 	intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9739ef525e13..df43b9eb5374 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1271,7 +1271,7 @@ 
 #define _TRANS_VRR_STATUS_B		0x6142C
 #define _TRANS_VRR_STATUS_C		0x6242C
 #define _TRANS_VRR_STATUS_D		0x6342C
-#define TRANS_VRR_STATUS(trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
+#define TRANS_VRR_STATUS(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
 #define   VRR_STATUS_VMAX_REACHED	REG_BIT(31)
 #define   VRR_STATUS_NOFLIP_TILL_BNDR	REG_BIT(30)
 #define   VRR_STATUS_FLIP_BEF_BNDR	REG_BIT(29)