| Message ID | 5abb076e8a8f78bf1e13a08d8300d2f7cc043cac.1670311877.git.aravind.iddamsetty@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/4] drm/i915/mtl: Define MOCS and PAT tables for MTL | expand |
On Tue, Dec 06, 2022 at 01:07:27PM +0530, Aravind Iddamsetty wrote: > New platforms will use different encode functions. You may want to elaborate slightly. E.g., something like "Future patches will introduce new platform-specific page table entry encoding functions. Existing PTE encoding calls should call the appropriate function through the VM's function pointer instead of hardcoding calls to the 'gen8' variants." With a tweaked commit message, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dpt.c | 2 +- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 10 +++++----- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++-- > 3 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c > index ad1a37b515fb..cb8ed9bfb240 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpt.c > +++ b/drivers/gpu/drm/i915/display/intel_dpt.c > @@ -298,7 +298,7 @@ intel_dpt_create(struct intel_framebuffer *fb) > vm->vma_ops.bind_vma = dpt_bind_vma; > vm->vma_ops.unbind_vma = dpt_unbind_vma; > > - vm->pte_encode = gen8_ggtt_pte_encode; > + vm->pte_encode = vm->gt->ggtt->vm.pte_encode; > > dpt->obj = dpt_obj; > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index 4daaa6f55668..31e838eee2ef 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -427,7 +427,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, > u32 flags) > { > struct i915_page_directory *pd; > - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags); > + const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level, flags); > gen8_pte_t *vaddr; > > pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2)); > @@ -580,7 +580,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, > enum i915_cache_level cache_level, > u32 flags) > { > - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags); > + const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags); > unsigned int rem = sg_dma_len(iter->sg); > u64 start = vma_res->start; > > @@ -743,7 +743,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm, > GEM_BUG_ON(pt->is_compact); > > vaddr = px_vaddr(pt); > - vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags); > + vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags); > drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); > } > > @@ -773,7 +773,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm, > } > > vaddr = px_vaddr(pt); > - vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags); > + vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level, flags); > } > > static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm, > @@ -820,7 +820,7 @@ static int gen8_init_scratch(struct i915_address_space *vm) > pte_flags |= PTE_LM; > > vm->scratch[0]->encode = > - gen8_pte_encode(px_dma(vm->scratch[0]), > + vm->pte_encode(px_dma(vm->scratch[0]), > I915_CACHE_NONE, pte_flags); > > for (i = 1; i <= vm->top; i++) { > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > index 7644738b9cdb..82203ad85b0e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > @@ -273,7 +273,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm, > gen8_pte_t __iomem *pte = > (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE; > > - gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags)); > + gen8_set_pte(pte, ggtt->vm.pte_encode(addr, level, flags)); > > ggtt->invalidate(ggtt); > } > @@ -283,8 +283,8 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, > enum i915_cache_level level, > u32 flags) > { > - const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags); > struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); > + const gen8_pte_t pte_encode = ggtt->vm.pte_encode(0, level, flags); > gen8_pte_t __iomem *gte; > gen8_pte_t __iomem *end; > struct sgt_iter iter; > -- > 2.25.1 >
On 07-12-2022 04:21, Matt Roper wrote: > On Tue, Dec 06, 2022 at 01:07:27PM +0530, Aravind Iddamsetty wrote: >> New platforms will use different encode functions. > > You may want to elaborate slightly. E.g., something like > > "Future patches will introduce new platform-specific page table entry > encoding functions. Existing PTE encoding calls should call the > appropriate function through the VM's function pointer instead of > hardcoding calls to the 'gen8' variants." > > With a tweaked commit message > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Thank You. Regards, Aravind. > >> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com> >> Cc: Matt Roper <matthew.d.roper@intel.com> >> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_dpt.c | 2 +- >> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 10 +++++----- >> drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++-- >> 3 files changed, 8 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c >> index ad1a37b515fb..cb8ed9bfb240 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dpt.c >> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c >> @@ -298,7 +298,7 @@ intel_dpt_create(struct intel_framebuffer *fb) >> vm->vma_ops.bind_vma = dpt_bind_vma; >> vm->vma_ops.unbind_vma = dpt_unbind_vma; >> >> - vm->pte_encode = gen8_ggtt_pte_encode; >> + vm->pte_encode = vm->gt->ggtt->vm.pte_encode; >> >> dpt->obj = dpt_obj; >> >> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c >> index 4daaa6f55668..31e838eee2ef 100644 >> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c >> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c >> @@ -427,7 +427,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, >> u32 flags) >> { >> struct i915_page_directory *pd; >> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags); >> + const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level, flags); >> gen8_pte_t *vaddr; >> >> pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2)); >> @@ -580,7 +580,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, >> enum i915_cache_level cache_level, >> u32 flags) >> { >> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags); >> + const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags); >> unsigned int rem = sg_dma_len(iter->sg); >> u64 start = vma_res->start; >> >> @@ -743,7 +743,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm, >> GEM_BUG_ON(pt->is_compact); >> >> vaddr = px_vaddr(pt); >> - vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags); >> + vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags); >> drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); >> } >> >> @@ -773,7 +773,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm, >> } >> >> vaddr = px_vaddr(pt); >> - vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags); >> + vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level, flags); >> } >> >> static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm, >> @@ -820,7 +820,7 @@ static int gen8_init_scratch(struct i915_address_space *vm) >> pte_flags |= PTE_LM; >> >> vm->scratch[0]->encode = >> - gen8_pte_encode(px_dma(vm->scratch[0]), >> + vm->pte_encode(px_dma(vm->scratch[0]), >> I915_CACHE_NONE, pte_flags); >> >> for (i = 1; i <= vm->top; i++) { >> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c >> index 7644738b9cdb..82203ad85b0e 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c >> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c >> @@ -273,7 +273,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm, >> gen8_pte_t __iomem *pte = >> (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE; >> >> - gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags)); >> + gen8_set_pte(pte, ggtt->vm.pte_encode(addr, level, flags)); >> >> ggtt->invalidate(ggtt); >> } >> @@ -283,8 +283,8 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, >> enum i915_cache_level level, >> u32 flags) >> { >> - const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags); >> struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); >> + const gen8_pte_t pte_encode = ggtt->vm.pte_encode(0, level, flags); >> gen8_pte_t __iomem *gte; >> gen8_pte_t __iomem *end; >> struct sgt_iter iter; >> -- >> 2.25.1 >> >
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index ad1a37b515fb..cb8ed9bfb240 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -298,7 +298,7 @@ intel_dpt_create(struct intel_framebuffer *fb) vm->vma_ops.bind_vma = dpt_bind_vma; vm->vma_ops.unbind_vma = dpt_unbind_vma; - vm->pte_encode = gen8_ggtt_pte_encode; + vm->pte_encode = vm->gt->ggtt->vm.pte_encode; dpt->obj = dpt_obj; diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 4daaa6f55668..31e838eee2ef 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -427,7 +427,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, u32 flags) { struct i915_page_directory *pd; - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags); + const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level, flags); gen8_pte_t *vaddr; pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2)); @@ -580,7 +580,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, enum i915_cache_level cache_level, u32 flags) { - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags); + const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags); unsigned int rem = sg_dma_len(iter->sg); u64 start = vma_res->start; @@ -743,7 +743,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm, GEM_BUG_ON(pt->is_compact); vaddr = px_vaddr(pt); - vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags); + vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags); drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); } @@ -773,7 +773,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm, } vaddr = px_vaddr(pt); - vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags); + vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level, flags); } static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm, @@ -820,7 +820,7 @@ static int gen8_init_scratch(struct i915_address_space *vm) pte_flags |= PTE_LM; vm->scratch[0]->encode = - gen8_pte_encode(px_dma(vm->scratch[0]), + vm->pte_encode(px_dma(vm->scratch[0]), I915_CACHE_NONE, pte_flags); for (i = 1; i <= vm->top; i++) { diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 7644738b9cdb..82203ad85b0e 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -273,7 +273,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm, gen8_pte_t __iomem *pte = (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE; - gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags)); + gen8_set_pte(pte, ggtt->vm.pte_encode(addr, level, flags)); ggtt->invalidate(ggtt); } @@ -283,8 +283,8 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, enum i915_cache_level level, u32 flags) { - const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags); struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); + const gen8_pte_t pte_encode = ggtt->vm.pte_encode(0, level, flags); gen8_pte_t __iomem *gte; gen8_pte_t __iomem *end; struct sgt_iter iter;
New platforms will use different encode functions. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> --- drivers/gpu/drm/i915/display/intel_dpt.c | 2 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 10 +++++----- drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-)