diff mbox series

[4/8] drm/i915/pcode: Add a couple of pcode helpers

Message ID 5b1cfcd6fc47dcc3d6aa9ed2f4412e7b6bf1159c.1649871650.git.ashutosh.dixit@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Media freq factor and per-gt enhancements/fixes | expand

Commit Message

Ashutosh Dixit April 13, 2022, 6:11 p.m. UTC 
Add a couple of helpers to help formatting pcode commands and improve code
readability.

Cc: Mike Ruhl <michael.j.ruhl@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Original-author: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |  3 +++
 drivers/gpu/drm/i915/intel_pcode.c | 32 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pcode.h | 12 +++++++++++
 3 files changed, 47 insertions(+)

Comments

Rodrigo Vivi April 15, 2022, 10:31 a.m. UTC | #1 
On Wed, Apr 13, 2022 at 11:11:05AM -0700, Ashutosh Dixit wrote:
> Add a couple of helpers to help formatting pcode commands and improve code
> readability.
> 
> Cc: Mike Ruhl <michael.j.ruhl@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Original-author: Dale B Stimson <dale.b.stimson@intel.com>

The right thing to do here is to git commit --amend --author="Dale B Stimson <dale.b.stimson@intel.com>"
probably also good to reset the date with --date...

> Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

and keep your signed-off-by here as well...

and also feel free add my rv-b after the author is fixed

Thanks,
Rodrigo.

> ---
>  drivers/gpu/drm/i915/i915_reg.h    |  3 +++
>  drivers/gpu/drm/i915/intel_pcode.c | 32 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pcode.h | 12 +++++++++++
>  3 files changed, 47 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fef71b242706..0d5a4ecd374a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6684,6 +6684,9 @@
>  
>  #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
>  #define   GEN6_PCODE_READY			(1 << 31)
> +#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
> +#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
> +#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
>  #define   GEN6_PCODE_ERROR_MASK			0xFF
>  #define     GEN6_PCODE_SUCCESS			0x0
>  #define     GEN6_PCODE_ILLEGAL_CMD		0x1
> diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
> index 0cff212cc81b..87b9f5035741 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.c
> +++ b/drivers/gpu/drm/i915/intel_pcode.c
> @@ -239,3 +239,35 @@ int intel_pcode_init(struct drm_i915_private *i915)
>  
>  	return 0;
>  }
> +
> +int __intel_gt_pcode_read(struct intel_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 *val)
> +{
> +	intel_wakeref_t wakeref;
> +	u32 mbox;
> +	int err;
> +
> +	mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
> +		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
> +		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
> +
> +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +		err = intel_gt_pcode_read(gt, mbox, val, NULL);
> +
> +	return err;
> +}
> +
> +int __intel_gt_pcode_write(struct intel_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 val)
> +{
> +	intel_wakeref_t wakeref;
> +	u32 mbox;
> +	int err;
> +
> +	mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
> +		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
> +		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
> +
> +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +		err = intel_gt_pcode_write(gt, mbox, val);
> +
> +	return err;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
> index 96c954ec91f9..65175d82e033 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.h
> +++ b/drivers/gpu/drm/i915/intel_pcode.h
> @@ -36,4 +36,16 @@ int intel_gt_pcode_request(struct intel_gt *gt, u32 mbox, u32 request,
>  
>  int intel_pcode_init(struct drm_i915_private *i915);
>  
> +/*
> + * Helpers for dGfx PCODE mailbox command formatting
> + */
> +int __intel_gt_pcode_read(struct intel_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 *val);
> +int __intel_gt_pcode_write(struct intel_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 val);
> +
> +#define __snb_pcode_read(i915, mbcmd, p1, p2, val) \
> +	__intel_gt_pcode_read(&(i915)->gt0, mbcmd, p1, p2, val)
> +
> +#define __snb_pcode_write(i915, mbcmd, p1, p2, val) \
> +	__intel_gt_pcode_write(&(i915)->gt0, mbcmd, p1, p2, val)
> +
>  #endif /* _INTEL_PCODE_H */
> -- 
> 2.34.1
>
Ashutosh Dixit April 19, 2022, 1:23 a.m. UTC | #2 
On Fri, 15 Apr 2022 03:31:19 -0700, Rodrigo Vivi wrote:
>
> On Wed, Apr 13, 2022 at 11:11:05AM -0700, Ashutosh Dixit wrote:
> > Add a couple of helpers to help formatting pcode commands and improve code
> > readability.
> >
> > Cc: Mike Ruhl <michael.j.ruhl@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Original-author: Dale B Stimson <dale.b.stimson@intel.com>
>
> The right thing to do here is to git commit --amend --author="Dale B Stimson <dale.b.stimson@intel.com>"
> probably also good to reset the date with --date...
>
> > Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> and keep your signed-off-by here as well...
>
> and also feel free add my rv-b after the author is fixed

Thanks, will fix the author in v2, two patches have this issue.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fef71b242706..0d5a4ecd374a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6684,6 +6684,9 @@ 
 
 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
 #define   GEN6_PCODE_READY			(1 << 31)
+#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
+#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
+#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
 #define   GEN6_PCODE_ERROR_MASK			0xFF
 #define     GEN6_PCODE_SUCCESS			0x0
 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index 0cff212cc81b..87b9f5035741 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -239,3 +239,35 @@  int intel_pcode_init(struct drm_i915_private *i915)
 
 	return 0;
 }
+
+int __intel_gt_pcode_read(struct intel_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 *val)
+{
+	intel_wakeref_t wakeref;
+	u32 mbox;
+	int err;
+
+	mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+		err = intel_gt_pcode_read(gt, mbox, val, NULL);
+
+	return err;
+}
+
+int __intel_gt_pcode_write(struct intel_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 val)
+{
+	intel_wakeref_t wakeref;
+	u32 mbox;
+	int err;
+
+	mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+		| REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+		err = intel_gt_pcode_write(gt, mbox, val);
+
+	return err;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 96c954ec91f9..65175d82e033 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -36,4 +36,16 @@  int intel_gt_pcode_request(struct intel_gt *gt, u32 mbox, u32 request,
 
 int intel_pcode_init(struct drm_i915_private *i915);
 
+/*
+ * Helpers for dGfx PCODE mailbox command formatting
+ */
+int __intel_gt_pcode_read(struct intel_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 *val);
+int __intel_gt_pcode_write(struct intel_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 val);
+
+#define __snb_pcode_read(i915, mbcmd, p1, p2, val) \
+	__intel_gt_pcode_read(&(i915)->gt0, mbcmd, p1, p2, val)
+
+#define __snb_pcode_write(i915, mbcmd, p1, p2, val) \
+	__intel_gt_pcode_write(&(i915)->gt0, mbcmd, p1, p2, val)
+
 #endif /* _INTEL_PCODE_H */