From patchwork Thu Dec 19 21:33:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13915861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2334AE7718B for ; Thu, 19 Dec 2024 21:35:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4AD410EDD6; Thu, 19 Dec 2024 21:35:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cv3Cd+kq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id D7A2510EDD5; Thu, 19 Dec 2024 21:35:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734644105; x=1766180105; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=edKFT1y3A0fWWuc+3x4xZnEGojYsGE81BeI+V9Ai3pQ=; b=cv3Cd+kq9fkjqI517SnGsKStIDVDVeOIukls+NgqXDB/xhgeIj6PN20r xvNgI41uCiK5pTwqVjf00VkazptPZC/zyaLOruzJMCJReQtjP0eHH7EG8 a+8DeRH3vELs8eydcmmL1HaJfxE9bnZvbb1UFnpTsBfu0KHOey8WFYhkA 2VKWl28eGHEryjqpXXvx8hSHyUcn1HQ50dhoQVr+/KZ/paYG69u1jkYw+ BoEhTQE645/Sa1GH2uoMNWmcT8G/WLJ7316egmp2Yu5Gric8UI5/OA9WW W8JOvv7Qh7bBOCnEJFK/rK3giGs8W1S1tK3VkvJ9h+ssTCWy7k9gKttsP g==; X-CSE-ConnectionGUID: haEsyZJNT0CJvfbvWNpqLw== X-CSE-MsgGUID: VpJ70/OMTe24wncQtzqIBQ== X-IronPort-AV: E=McAfee;i="6700,10204,11291"; a="35330589" X-IronPort-AV: E=Sophos;i="6.12,248,1728975600"; d="scan'208";a="35330589" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 13:35:05 -0800 X-CSE-ConnectionGUID: gqKPt9KLQ9uIwfEIdJTyvg== X-CSE-MsgGUID: kAv8U2ToRcKfzbByZ+rzqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,248,1728975600"; d="scan'208";a="98115742" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.207]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 13:35:02 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, imre.deak@intel.com Subject: [PATCH v2 09/16] drm/i915/ddi: 128b/132b SST also needs DP_TP_CTL_MODE_MST Date: Thu, 19 Dec 2024 23:33:58 +0200 Message-Id: <600a928f06d7c77b7b10672b7e09e083caa72c0c.1734643485.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It's not very clearly specified, and the hardware bit is ill-named, but 128b/132b SST also needs the MST mode set in the DP_TP_CTL register. This is preparation for enabling 128b/132b SST. This path is not reachable yet. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ce34a619d48a..6f813bf85b23 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3656,7 +3656,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || + intel_dp_is_uhbr(crtc_state)) { dp_tp_ctl |= DP_TP_CTL_MODE_MST; } else { dp_tp_ctl |= DP_TP_CTL_MODE_SST; @@ -3716,7 +3717,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, } dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || + intel_dp_is_uhbr(crtc_state)) { dp_tp_ctl |= DP_TP_CTL_MODE_MST; } else { dp_tp_ctl |= DP_TP_CTL_MODE_SST;