@@ -2558,12 +2558,12 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
int ret;
i915_gem_object_flush_gpu_write_domain(obj);
- i915_gem_object_flush_gtt_write_domain(obj);
ret = i915_gem_object_wait_rendering(obj);
if (ret != 0)
return ret;
}
+ i915_gem_object_flush_gtt_write_domain(obj);
i915_gem_clear_fence_reg (obj);
return 0;
@@ -2733,6 +2733,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
static void
i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
{
+ drm_i915_private_t *dev_priv = obj->dev->dev_private;
uint32_t old_write_domain;
if (obj->write_domain != I915_GEM_DOMAIN_GTT)
@@ -2741,7 +2742,11 @@ i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
/* No actual flushing is required for the GTT write domain. Writes
* to it immediately go to main memory as far as we know, so there's
* no chipset flush. It also doesn't land in render cache.
+ * But flush the wc cache on the CPU. For otherwise the fence teardown
+ * for tiled buffers is not synchronized with any outstanding writes.
*/
+ I915_READ(IMR);
+
old_write_domain = obj->write_domain;
obj->write_domain = 0;