| Message ID | 782fea69f6daff6586fbde991bbf026dc36e6c7b.1547629303.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: switch to kernel fixed size types | expand |
On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote: > Mixed C99 and kernel types use is getting ugly. Prefer kernel types. > > sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 104 +++++++++++++---------- > ---- > 1 file changed, 52 insertions(+), 52 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index af164d712e9e..b3d6ee7eee0e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -49,7 +49,7 @@ > #include <linux/reservation.h> > > /* Primary plane formats for gen <= 3 */ > -static const uint32_t i8xx_primary_formats[] = { > +static const u32 i8xx_primary_formats[] = { > DRM_FORMAT_C8, > DRM_FORMAT_RGB565, > DRM_FORMAT_XRGB1555, > @@ -57,7 +57,7 @@ static const uint32_t i8xx_primary_formats[] = { > }; > > /* Primary plane formats for gen >= 4 */ > -static const uint32_t i965_primary_formats[] = { > +static const u32 i965_primary_formats[] = { > DRM_FORMAT_C8, > DRM_FORMAT_RGB565, > DRM_FORMAT_XRGB8888, > @@ -66,18 +66,18 @@ static const uint32_t i965_primary_formats[] = { > DRM_FORMAT_XBGR2101010, > }; > > -static const uint64_t i9xx_format_modifiers[] = { > +static const u64 i9xx_format_modifiers[] = { > I915_FORMAT_MOD_X_TILED, > DRM_FORMAT_MOD_LINEAR, > DRM_FORMAT_MOD_INVALID > }; > > /* Cursor formats */ > -static const uint32_t intel_cursor_formats[] = { > +static const u32 intel_cursor_formats[] = { > DRM_FORMAT_ARGB8888, > }; > > -static const uint64_t cursor_format_modifiers[] = { > +static const u64 cursor_format_modifiers[] = { > DRM_FORMAT_MOD_LINEAR, > DRM_FORMAT_MOD_INVALID > }; > @@ -493,7 +493,7 @@ static int pnv_calc_dpll_params(int refclk, > struct dpll *clock) > return clock->dot; > } > > -static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) > +static u32 i9xx_dpll_compute_m(struct dpll *dpll) > { > return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); > } > @@ -528,8 +528,8 @@ int chv_calc_dpll_params(int refclk, struct dpll > *clock) > clock->p = clock->p1 * clock->p2; > if (WARN_ON(clock->n == 0 || clock->p == 0)) > return 0; > - clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, > - clock->n << 22); > + clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m, > + clock->n << 22); > clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); > > return clock->dot / 5; > @@ -891,7 +891,7 @@ chv_find_best_dpll(const struct intel_limit > *limit, > struct drm_device *dev = crtc->base.dev; > unsigned int best_error_ppm; > struct dpll clock; > - uint64_t m2; > + u64 m2; > int found = false; > > memset(best_clock, 0, sizeof(*best_clock)); > @@ -913,7 +913,7 @@ chv_find_best_dpll(const struct intel_limit > *limit, > > clock.p = clock.p1 * clock.p2; > > - m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * > clock.p * > + m2 = DIV_ROUND_CLOSEST_ULL(((u64)target * > clock.p * > clock.n) << 22, refclk * > clock.m1); > > if (m2 > INT_MAX/clock.m1) > @@ -1610,7 +1610,7 @@ static void > ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > i915_reg_t reg; > - uint32_t val, pipeconf_val; > + u32 val, pipeconf_val; > > /* Make sure PCH DPLL is enabled */ > assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); > @@ -1698,7 +1698,7 @@ static void > ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, > enum pipe pipe) > { > i915_reg_t reg; > - uint32_t val; > + u32 val; > > /* FDI relies on the transcoder */ > assert_fdi_tx_disabled(dev_priv, pipe); > @@ -2375,7 +2375,7 @@ static int intel_fb_offset_to_xy(int *x, int > *y, > return 0; > } > > -static unsigned int intel_fb_modifier_to_tiling(uint64_t > fb_modifier) > +static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) > { > switch (fb_modifier) { > case I915_FORMAT_MOD_X_TILED: > @@ -3507,7 +3507,7 @@ u32 skl_plane_stride(const struct > intel_plane_state *plane_state, > return stride / skl_plane_stride_mult(fb, color_plane, > rotation); > } > > -static u32 skl_plane_ctl_format(uint32_t pixel_format) > +static u32 skl_plane_ctl_format(u32 pixel_format) > { > switch (pixel_format) { > case DRM_FORMAT_C8: > @@ -3577,7 +3577,7 @@ static u32 glk_plane_color_ctl_alpha(const > struct intel_plane_state *plane_state > } > } > > -static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) > +static u32 skl_plane_ctl_tiling(u64 fb_modifier) > { > switch (fb_modifier) { > case DRM_FORMAT_MOD_LINEAR: > @@ -4597,7 +4597,7 @@ static void > ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *c > > static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private > *dev_priv, bool enable) > { > - uint32_t temp; > + u32 temp; > > temp = I915_READ(SOUTH_CHICKEN1); > if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) > @@ -5720,7 +5720,7 @@ static void icl_pipe_mbus_enable(struct > intel_crtc *crtc) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > - uint32_t val; > + u32 val; > > val = MBUS_DBOX_A_CREDIT(2); > val |= MBUS_DBOX_BW_CREDIT(1); > @@ -6624,9 +6624,9 @@ static bool > intel_crtc_supports_double_wide(const struct intel_crtc *crtc) > (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); > } > > -static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state > *pipe_config) > +static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state > *pipe_config) > { > - uint32_t pixel_rate; > + u32 pixel_rate; > > pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; > > @@ -6636,8 +6636,8 @@ static uint32_t ilk_pipe_pixel_rate(const > struct intel_crtc_state *pipe_config) > */ > > if (pipe_config->pch_pfit.enabled) { > - uint64_t pipe_w, pipe_h, pfit_w, pfit_h; > - uint32_t pfit_size = pipe_config->pch_pfit.size; > + u64 pipe_w, pipe_h, pfit_w, pfit_h; > + u32 pfit_size = pipe_config->pch_pfit.size; > > pipe_w = pipe_config->pipe_src_w; > pipe_h = pipe_config->pipe_src_h; > @@ -6652,7 +6652,7 @@ static uint32_t ilk_pipe_pixel_rate(const > struct intel_crtc_state *pipe_config) > if (WARN_ON(!pfit_w || !pfit_h)) > return pixel_rate; > > - pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * > pipe_h, > + pixel_rate = div_u64((u64)pixel_rate * pipe_w * pipe_h, > pfit_w * pfit_h); > } > > @@ -6748,7 +6748,7 @@ static int intel_crtc_compute_config(struct > intel_crtc *crtc, > } > > static void > -intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) > +intel_reduce_m_n_ratio(u32 *num, u32 *den) > { > while (*num > DATA_LINK_M_N_MASK || > *den > DATA_LINK_M_N_MASK) { > @@ -6758,7 +6758,7 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t > *den) > } > > static void compute_m_n(unsigned int m, unsigned int n, > - uint32_t *ret_m, uint32_t *ret_n, > + u32 *ret_m, u32 *ret_n, > bool constant_n) > { > /* > @@ -6773,7 +6773,7 @@ static void compute_m_n(unsigned int m, > unsigned int n, > else > *ret_n = min_t(unsigned int, roundup_pow_of_two(n), > DATA_LINK_N_MAX); > > - *ret_m = div_u64((uint64_t) m * *ret_n, n); > + *ret_m = div_u64((u64)m * *ret_n, n); > intel_reduce_m_n_ratio(ret_m, ret_n); > } > > @@ -6803,12 +6803,12 @@ static inline bool intel_panel_use_ssc(struct > drm_i915_private *dev_priv) > && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); > } > > -static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) > +static u32 pnv_dpll_compute_fp(struct dpll *dpll) > { > return (1 << dpll->n) << 16 | dpll->m2; > } > > -static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) > +static u32 i9xx_dpll_compute_fp(struct dpll *dpll) > { > return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; > } > @@ -7364,7 +7364,7 @@ static void intel_set_pipe_timings(const struct > intel_crtc_state *crtc_state) > enum pipe pipe = crtc->pipe; > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > const struct drm_display_mode *adjusted_mode = &crtc_state- > >base.adjusted_mode; > - uint32_t crtc_vtotal, crtc_vblank_end; > + u32 crtc_vtotal, crtc_vblank_end; > int vsyncshift = 0; > > /* We need to be careful not to changed the adjusted mode, for > otherwise > @@ -7439,7 +7439,7 @@ static void intel_get_pipe_timings(struct > intel_crtc *crtc, > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; > - uint32_t tmp; > + u32 tmp; > > tmp = I915_READ(HTOTAL(cpu_transcoder)); > pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) > + 1; > @@ -7510,7 +7510,7 @@ static void i9xx_set_pipeconf(const struct > intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - uint32_t pipeconf; > + u32 pipeconf; > > pipeconf = 0; > > @@ -7755,7 +7755,7 @@ static void i9xx_get_pfit_config(struct > intel_crtc *crtc, > struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - uint32_t tmp; > + u32 tmp; > > if (INTEL_GEN(dev_priv) <= 3 && > (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) > @@ -7971,7 +7971,7 @@ static bool i9xx_get_pipe_config(struct > intel_crtc *crtc, > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum intel_display_power_domain power_domain; > intel_wakeref_t wakeref; > - uint32_t tmp; > + u32 tmp; > bool ret; > > power_domain = POWER_DOMAIN_PIPE(crtc->pipe); > @@ -8251,7 +8251,7 @@ static void ironlake_init_pch_refclk(struct > drm_i915_private *dev_priv) > > static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) > { > - uint32_t tmp; > + u32 tmp; > > tmp = I915_READ(SOUTH_CHICKEN2); > tmp |= FDI_MPHY_IOSFSB_RESET_CTL; > @@ -8273,7 +8273,7 @@ static void lpt_reset_fdi_mphy(struct > drm_i915_private *dev_priv) > /* WaMPhyProgramming:hsw */ > static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) > { > - uint32_t tmp; > + u32 tmp; > > tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); > tmp &= ~(0xFF << 24); > @@ -8354,7 +8354,7 @@ static void lpt_program_fdi_mphy(struct > drm_i915_private *dev_priv) > static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, > bool with_spread, bool with_fdi) > { > - uint32_t reg, tmp; > + u32 reg, tmp; > > if (WARN(with_fdi && !with_spread, "FDI requires > downspread\n")) > with_spread = true; > @@ -8393,7 +8393,7 @@ static void lpt_enable_clkout_dp(struct > drm_i915_private *dev_priv, > /* Sequence to disable CLKOUT_DP */ > static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) > { > - uint32_t reg, tmp; > + u32 reg, tmp; > > mutex_lock(&dev_priv->sb_lock); > > @@ -8418,7 +8418,7 @@ static void lpt_disable_clkout_dp(struct > drm_i915_private *dev_priv) > > #define BEND_IDX(steps) ((50 + (steps)) / 5) > > -static const uint16_t sscdivintphase[] = { > +static const u16 sscdivintphase[] = { > [BEND_IDX( 50)] = 0x3B23, > [BEND_IDX( 45)] = 0x3B23, > [BEND_IDX( 40)] = 0x3C23, > @@ -8450,7 +8450,7 @@ static const uint16_t sscdivintphase[] = { > */ > static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, > int steps) > { > - uint32_t tmp; > + u32 tmp; > int idx = BEND_IDX(steps); > > if (WARN_ON(steps % 5 != 0)) > @@ -8516,7 +8516,7 @@ static void ironlake_set_pipeconf(const struct > intel_crtc_state *crtc_state) > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > - uint32_t val; > + u32 val; > > val = 0; > > @@ -8863,7 +8863,7 @@ static void skylake_get_pfit_config(struct > intel_crtc *crtc, > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > struct intel_crtc_scaler_state *scaler_state = &pipe_config- > >scaler_state; > - uint32_t ps_ctrl = 0; > + u32 ps_ctrl = 0; > int id = -1; > int i; > > @@ -9019,7 +9019,7 @@ static void ironlake_get_pfit_config(struct > intel_crtc *crtc, > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > - uint32_t tmp; > + u32 tmp; > > tmp = I915_READ(PF_CTL(crtc->pipe)); > > @@ -9045,7 +9045,7 @@ static bool ironlake_get_pipe_config(struct > intel_crtc *crtc, > struct drm_i915_private *dev_priv = to_i915(dev); > enum intel_display_power_domain power_domain; > intel_wakeref_t wakeref; > - uint32_t tmp; > + u32 tmp; > bool ret; > > power_domain = POWER_DOMAIN_PIPE(crtc->pipe); > @@ -9173,7 +9173,7 @@ static void assert_can_disable_lcpll(struct > drm_i915_private *dev_priv) > I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs > enabled\n"); > } > > -static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) > +static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) > { > if (IS_HASWELL(dev_priv)) > return I915_READ(D_COMP_HSW); > @@ -9181,7 +9181,7 @@ static uint32_t hsw_read_dcomp(struct > drm_i915_private *dev_priv) > return I915_READ(D_COMP_BDW); > } > > -static void hsw_write_dcomp(struct drm_i915_private *dev_priv, > uint32_t val) > +static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 > val) > { > if (IS_HASWELL(dev_priv)) { > mutex_lock(&dev_priv->pcu_lock); > @@ -9206,7 +9206,7 @@ static void hsw_write_dcomp(struct > drm_i915_private *dev_priv, uint32_t val) > static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, > bool switch_to_fclk, bool > allow_power_down) > { > - uint32_t val; > + u32 val; > > assert_can_disable_lcpll(dev_priv); > > @@ -9253,7 +9253,7 @@ static void hsw_disable_lcpll(struct > drm_i915_private *dev_priv, > */ > static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) > { > - uint32_t val; > + u32 val; > > val = I915_READ(LCPLL_CTL); > > @@ -9328,7 +9328,7 @@ static void hsw_restore_lcpll(struct > drm_i915_private *dev_priv) > */ > void hsw_enable_pc8(struct drm_i915_private *dev_priv) > { > - uint32_t val; > + u32 val; > > DRM_DEBUG_KMS("Enabling package C8+\n"); > > @@ -9344,7 +9344,7 @@ void hsw_enable_pc8(struct drm_i915_private > *dev_priv) > > void hsw_disable_pc8(struct drm_i915_private *dev_priv) > { > - uint32_t val; > + u32 val; > > DRM_DEBUG_KMS("Disabling package C8+\n"); > > @@ -9466,7 +9466,7 @@ static void haswell_get_ddi_pll(struct > drm_i915_private *dev_priv, > struct intel_crtc_state *pipe_config) > { > enum intel_dpll_id id; > - uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); > + u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); > > switch (ddi_pll_sel) { > case PORT_CLK_SEL_WRPLL1: > @@ -9634,7 +9634,7 @@ static void haswell_get_ddi_port_state(struct > intel_crtc *crtc, > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct intel_shared_dpll *pll; > enum port port; > - uint32_t tmp; > + u32 tmp; > > tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config- > >cpu_transcoder)); > > @@ -13751,8 +13751,8 @@ intel_legacy_cursor_update(struct drm_plane > *plane, > struct drm_framebuffer *fb, > int crtc_x, int crtc_y, > unsigned int crtc_w, unsigned int crtc_h, > - uint32_t src_x, uint32_t src_y, > - uint32_t src_w, uint32_t src_h, > + u32 src_x, u32 src_y, > + u32 src_w, u32 src_h, > struct drm_modeset_acquire_ctx *ctx) > { > struct drm_i915_private *dev_priv = to_i915(crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index af164d712e9e..b3d6ee7eee0e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -49,7 +49,7 @@ #include <linux/reservation.h> /* Primary plane formats for gen <= 3 */ -static const uint32_t i8xx_primary_formats[] = { +static const u32 i8xx_primary_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, DRM_FORMAT_XRGB1555, @@ -57,7 +57,7 @@ static const uint32_t i8xx_primary_formats[] = { }; /* Primary plane formats for gen >= 4 */ -static const uint32_t i965_primary_formats[] = { +static const u32 i965_primary_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, @@ -66,18 +66,18 @@ static const uint32_t i965_primary_formats[] = { DRM_FORMAT_XBGR2101010, }; -static const uint64_t i9xx_format_modifiers[] = { +static const u64 i9xx_format_modifiers[] = { I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID }; /* Cursor formats */ -static const uint32_t intel_cursor_formats[] = { +static const u32 intel_cursor_formats[] = { DRM_FORMAT_ARGB8888, }; -static const uint64_t cursor_format_modifiers[] = { +static const u64 cursor_format_modifiers[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID }; @@ -493,7 +493,7 @@ static int pnv_calc_dpll_params(int refclk, struct dpll *clock) return clock->dot; } -static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) +static u32 i9xx_dpll_compute_m(struct dpll *dpll) { return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); } @@ -528,8 +528,8 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock) clock->p = clock->p1 * clock->p2; if (WARN_ON(clock->n == 0 || clock->p == 0)) return 0; - clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, - clock->n << 22); + clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m, + clock->n << 22); clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); return clock->dot / 5; @@ -891,7 +891,7 @@ chv_find_best_dpll(const struct intel_limit *limit, struct drm_device *dev = crtc->base.dev; unsigned int best_error_ppm; struct dpll clock; - uint64_t m2; + u64 m2; int found = false; memset(best_clock, 0, sizeof(*best_clock)); @@ -913,7 +913,7 @@ chv_find_best_dpll(const struct intel_limit *limit, clock.p = clock.p1 * clock.p2; - m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * + m2 = DIV_ROUND_CLOSEST_ULL(((u64)target * clock.p * clock.n) << 22, refclk * clock.m1); if (m2 > INT_MAX/clock.m1) @@ -1610,7 +1610,7 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; i915_reg_t reg; - uint32_t val, pipeconf_val; + u32 val, pipeconf_val; /* Make sure PCH DPLL is enabled */ assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); @@ -1698,7 +1698,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, enum pipe pipe) { i915_reg_t reg; - uint32_t val; + u32 val; /* FDI relies on the transcoder */ assert_fdi_tx_disabled(dev_priv, pipe); @@ -2375,7 +2375,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, return 0; } -static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) +static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) { switch (fb_modifier) { case I915_FORMAT_MOD_X_TILED: @@ -3507,7 +3507,7 @@ u32 skl_plane_stride(const struct intel_plane_state *plane_state, return stride / skl_plane_stride_mult(fb, color_plane, rotation); } -static u32 skl_plane_ctl_format(uint32_t pixel_format) +static u32 skl_plane_ctl_format(u32 pixel_format) { switch (pixel_format) { case DRM_FORMAT_C8: @@ -3577,7 +3577,7 @@ static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state } } -static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) +static u32 skl_plane_ctl_tiling(u64 fb_modifier) { switch (fb_modifier) { case DRM_FORMAT_MOD_LINEAR: @@ -4597,7 +4597,7 @@ static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *c static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable) { - uint32_t temp; + u32 temp; temp = I915_READ(SOUTH_CHICKEN1); if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) @@ -5720,7 +5720,7 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - uint32_t val; + u32 val; val = MBUS_DBOX_A_CREDIT(2); val |= MBUS_DBOX_BW_CREDIT(1); @@ -6624,9 +6624,9 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); } -static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) +static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) { - uint32_t pixel_rate; + u32 pixel_rate; pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; @@ -6636,8 +6636,8 @@ static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) */ if (pipe_config->pch_pfit.enabled) { - uint64_t pipe_w, pipe_h, pfit_w, pfit_h; - uint32_t pfit_size = pipe_config->pch_pfit.size; + u64 pipe_w, pipe_h, pfit_w, pfit_h; + u32 pfit_size = pipe_config->pch_pfit.size; pipe_w = pipe_config->pipe_src_w; pipe_h = pipe_config->pipe_src_h; @@ -6652,7 +6652,7 @@ static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) if (WARN_ON(!pfit_w || !pfit_h)) return pixel_rate; - pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, + pixel_rate = div_u64((u64)pixel_rate * pipe_w * pipe_h, pfit_w * pfit_h); } @@ -6748,7 +6748,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, } static void -intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) +intel_reduce_m_n_ratio(u32 *num, u32 *den) { while (*num > DATA_LINK_M_N_MASK || *den > DATA_LINK_M_N_MASK) { @@ -6758,7 +6758,7 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) } static void compute_m_n(unsigned int m, unsigned int n, - uint32_t *ret_m, uint32_t *ret_n, + u32 *ret_m, u32 *ret_n, bool constant_n) { /* @@ -6773,7 +6773,7 @@ static void compute_m_n(unsigned int m, unsigned int n, else *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); - *ret_m = div_u64((uint64_t) m * *ret_n, n); + *ret_m = div_u64((u64)m * *ret_n, n); intel_reduce_m_n_ratio(ret_m, ret_n); } @@ -6803,12 +6803,12 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); } -static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) +static u32 pnv_dpll_compute_fp(struct dpll *dpll) { return (1 << dpll->n) << 16 | dpll->m2; } -static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) +static u32 i9xx_dpll_compute_fp(struct dpll *dpll) { return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; } @@ -7364,7 +7364,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; - uint32_t crtc_vtotal, crtc_vblank_end; + u32 crtc_vtotal, crtc_vblank_end; int vsyncshift = 0; /* We need to be careful not to changed the adjusted mode, for otherwise @@ -7439,7 +7439,7 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; - uint32_t tmp; + u32 tmp; tmp = I915_READ(HTOTAL(cpu_transcoder)); pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; @@ -7510,7 +7510,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - uint32_t pipeconf; + u32 pipeconf; pipeconf = 0; @@ -7755,7 +7755,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - uint32_t tmp; + u32 tmp; if (INTEL_GEN(dev_priv) <= 3 && (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) @@ -7971,7 +7971,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; - uint32_t tmp; + u32 tmp; bool ret; power_domain = POWER_DOMAIN_PIPE(crtc->pipe); @@ -8251,7 +8251,7 @@ static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) { - uint32_t tmp; + u32 tmp; tmp = I915_READ(SOUTH_CHICKEN2); tmp |= FDI_MPHY_IOSFSB_RESET_CTL; @@ -8273,7 +8273,7 @@ static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) /* WaMPhyProgramming:hsw */ static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) { - uint32_t tmp; + u32 tmp; tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); tmp &= ~(0xFF << 24); @@ -8354,7 +8354,7 @@ static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, bool with_spread, bool with_fdi) { - uint32_t reg, tmp; + u32 reg, tmp; if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) with_spread = true; @@ -8393,7 +8393,7 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, /* Sequence to disable CLKOUT_DP */ static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) { - uint32_t reg, tmp; + u32 reg, tmp; mutex_lock(&dev_priv->sb_lock); @@ -8418,7 +8418,7 @@ static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) #define BEND_IDX(steps) ((50 + (steps)) / 5) -static const uint16_t sscdivintphase[] = { +static const u16 sscdivintphase[] = { [BEND_IDX( 50)] = 0x3B23, [BEND_IDX( 45)] = 0x3B23, [BEND_IDX( 40)] = 0x3C23, @@ -8450,7 +8450,7 @@ static const uint16_t sscdivintphase[] = { */ static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) { - uint32_t tmp; + u32 tmp; int idx = BEND_IDX(steps); if (WARN_ON(steps % 5 != 0)) @@ -8516,7 +8516,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - uint32_t val; + u32 val; val = 0; @@ -8863,7 +8863,7 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; - uint32_t ps_ctrl = 0; + u32 ps_ctrl = 0; int id = -1; int i; @@ -9019,7 +9019,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - uint32_t tmp; + u32 tmp; tmp = I915_READ(PF_CTL(crtc->pipe)); @@ -9045,7 +9045,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; - uint32_t tmp; + u32 tmp; bool ret; power_domain = POWER_DOMAIN_PIPE(crtc->pipe); @@ -9173,7 +9173,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); } -static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) +static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) { if (IS_HASWELL(dev_priv)) return I915_READ(D_COMP_HSW); @@ -9181,7 +9181,7 @@ static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) return I915_READ(D_COMP_BDW); } -static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) +static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) { if (IS_HASWELL(dev_priv)) { mutex_lock(&dev_priv->pcu_lock); @@ -9206,7 +9206,7 @@ static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, bool switch_to_fclk, bool allow_power_down) { - uint32_t val; + u32 val; assert_can_disable_lcpll(dev_priv); @@ -9253,7 +9253,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, */ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) { - uint32_t val; + u32 val; val = I915_READ(LCPLL_CTL); @@ -9328,7 +9328,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) */ void hsw_enable_pc8(struct drm_i915_private *dev_priv) { - uint32_t val; + u32 val; DRM_DEBUG_KMS("Enabling package C8+\n"); @@ -9344,7 +9344,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv) void hsw_disable_pc8(struct drm_i915_private *dev_priv) { - uint32_t val; + u32 val; DRM_DEBUG_KMS("Disabling package C8+\n"); @@ -9466,7 +9466,7 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, struct intel_crtc_state *pipe_config) { enum intel_dpll_id id; - uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); + u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); switch (ddi_pll_sel) { case PORT_CLK_SEL_WRPLL1: @@ -9634,7 +9634,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; enum port port; - uint32_t tmp; + u32 tmp; tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); @@ -13751,8 +13751,8 @@ intel_legacy_cursor_update(struct drm_plane *plane, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, - uint32_t src_x, uint32_t src_y, - uint32_t src_w, uint32_t src_h, + u32 src_x, u32 src_y, + u32 src_w, u32 src_h, struct drm_modeset_acquire_ctx *ctx) { struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Mixed C99 and kernel types use is getting ugly. Prefer kernel types. sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 104 +++++++++++++-------------- 1 file changed, 52 insertions(+), 52 deletions(-)